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Recent content by eddsos

  1. E

    Wu Yufei's MATLAB Turbo Code Reupload

    Thanks, I am trying to study this and design it using verilog.
  2. E

    A question about a differential amplifier design.

    Hello, using the follow spice netlist, V(6) = 0V when VID = 0V. But, what if I want V(6) = 1V when VID =0V. Which parameters should be adjusted? I changed VIC, but this seems have no effect. Thanks * *.lib 'E:\software\asmc\models\IC5.1.41\hspice\bc35hv_mod_hspice.lib' MOS_TT * VID 7 0 DC 0V...
  3. E

    help: about hspice simulation noise.

    Thank you very much! I found why. I misreading the parameter "input referred noise" Vrms and "input referred noise spectra".
  4. E

    help: about hspice simulation noise.

    help of spice simulation Hello, When I simulate amplifier circuit using hspice according IEEE papers, I got lower noise level(100x). Could some one tell me why? I need add background noise? What is the rule to add background noise? Thanks.
  5. E

    problems about formality constant reg

    formality problem I have one register in netlist, whose data input enable is always invalid. So, this register should be 0 after reset, which is a redundant logic. How can i let formality know this when compare downstream logics?
  6. E

    lint tools for verilog

    lint + verilog we do not use nlint tool alone either, when compile, the tool will check!
  7. E

    synthesis question on FSM, error on syntheis netlist!!

    That means the FSM will not be entered. Because your input is a constant!!! There is no meaning to design a FSM.
  8. E

    protocal T14 of ISO7816-3 of smartcard.

    smartcard t14 This means a protocal not defined by ISO. But I do not know how to implement it either. Could someone tell about it?
  9. E

    formal verification of Latch-based and DFF-based netlist

    Re: formal verification of Latch-based and DFF-based netli There is a setup parameter, which could make the tools recoginize the situation automatically. I don't remember it now. you can see the reference manual.
  10. E

    Some logic in golden design is lost in Verplex clock design

    help: clock in verplex? When using verplex, i found that some logic in golden design(rtl code) is lost, while revised design is right. I am confused and do not know what to do. Since the clock is generated by several input through combination logic, maybe I need setup come attribute on the...
  11. E

    HELP: one question about verplex.

    how to set up two black box are equal in verplex How to set up two black box are equal in verplex?
  12. E

    ask for datasheet about chips related with set-top box.

    I want to design set-top box. Any one has done this? I need some suggestion. Please send the datasheet to my mail box. I have no enough points to download. my email: lcf0451@yeah.net
  13. E

    Novas nLint can do what?

    novas.nlint "I use nLint to check RTL codes: 1. syntax 2. design error, include DFT, timing loop, mismatch between synthesis and simulation and synthesis error. And more, i use it to check my netlist sometimes." I don't understand the item 2. Could you describe it in detail?
  14. E

    question about clock generation

    some kind of CPLD could implemented the function.
  15. E

    Tool that generates layout from Spice netlist or Verilog code

    generate layout from verilog There are many tools for synthesis. But I do not understand why analog designer need them? If you can't read or design schematic directly, how can you be a analog desinger?
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