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Recent content by EDALIST

  1. E

    xilinx lattice high speed interface

    aurora is xilinx protocol it can be used only with other aurora cores.
  2. E

    verilog code copyright/ownership

    Franckly, if you give your sources, you can't protect them to be used by others.
  3. E

    Xilinx EDK 8.1i incompatible with ISE 8.2i?

    You Should Not Use Different Versions, Try To Upgrade Your EDK To 8.2.
  4. E

    Help me capture the address and data in a ram using Chipscope 8.1

    Re: about chipscope! i think you need to make sure your ila clock input is fast enought to sample the bus.
  5. E

    Help me solve an Ngdbuild error

    Re: Ngdbuild error seem you have a short circuit
  6. E

    receive five bytes from one-byte data bus in one clock cycle

    Re: receive five bytes from one-byte data bus in one clock c I Think The Easy Solution Is To Use 40 bit Bus.
  7. E

    is there any concurency remains using microblaze processor?

    Re: is there any concurency remains using microblaze process You Should Use The FSL ability Of The Micro-blaze. Build Your VHDL core And Interface It To Microblaze Thrught FSL. Then In One Command You Can Read The filterd Output.
  8. E

    Issues when reading from Microblaze I/O ports

    Re: Microblaze I/O ports the simple explenation is that since the bus is bidirectional bus, you just see the actual bus status, i.e other device drive the bus to '0'.
  9. E

    Interfacing with Microblaze

    YOU sHOULD cHECK tHAT yOUR xps IS A Sub - Module of your design. All IBUF, OBUF Should be on yout top level design.
  10. E

    Interfacing with Microblaze

    I Think Your Problem Is Ver Common When Interfacing XPS. The GPIO Is bi-Directional Bus. Thus GPIO Signal Is A Product Of OBUF Connected To GPIO_I (in) , GPIO_T (r/w~), GPIO_O (out) What You Realy Need Is To Connect This Signals Instead In XPS. Best Regards.
  11. E

    Interfacing with Microblaze

    just use the OPB_GPIO Core To Generate The I/O Port.
  12. E

    wut is microblaze? how can i attach my VHDL design to it?

    Re: wut is microblaze? how can i attach my VHDL design to it just goto xilinx **broken link removed**
  13. E

    Help me write a testbench of ITU656

    Re: problem about ITU656 just read the standard - are you interseted in pal or ntsc ? aother sources are the ebu and smpte equivalent stadards.
  14. E

    Interfacing with Microblaze

    you should rely more on your xps design. use the wizard to connect your logic to microblaze opb bus. another option is to maunaly create your microblaze core.
  15. E

    Why use FPGA not CPLD to interface high speed ADC

    fpga has more logic and ram memories. cpld if faster, but adc is not that fast even if it is high speed.
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