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Probably you could track your netlist where the nmos2v comes from. If you would like to modify your tsmc18rf lib, better make a copy and make your own lib. And re-define your model library setup in the Artist Environment.
ams+cunoun
You should create a config view first. When you run AMS, make sure to update your config view as long as you modify the schematic view. Be sure to re-netlist the design.
gmid_ruida.pdf
Good to see that people are still looking at gm/id stuff. A simple way is to plot in hspice. Originally I was trying to do it in Cadence while following Prof. Murmann's gm/id design methodology. You can setup the expression in the artist environment with calculator, and then plot...
1) Try to use a large R (not affect your BW) shunting with your feedback Cap if you use the real opamp. re-run the simulation to see what's the difference.
2) For your clock stimulus, make sure you are using 2 phase non-overlapping clocks. The non-overlapping period could be roughly 1-5% of...
Re: opa for bandgap
20uS Gm looks a little bit small. increase gm further.
1) on second look at your topology, you do not have to add second stage. If your supply permits, you can add a cascode for your bottom transistors, M3, M8, M9. Basically you are using a folded cascade ota, but without...
Re: opa for bandgap
If Your gain is 70dB, and -3dB BW is 400kHz, that may be okay. If your GBW is 400k, then not good for PSRR consideration.
For BG, the higher GBW is needed to supress power supply noise.
Re: question about to disconnect the loop of bandgap please
When breaking the loop, you usually add a large L and a large C (GH/GF) to form a LP filter. So it's connected in DC and disconnected in AC. In this case, it does not hurt to break Z.
Re: CDR lock requirement
Bandwidth of the CDR is trade-off between jitter transfer and input jitter tolerance if linear phase detector used. A difficult task.
When design a PLL chip, do you guys use an internal voltage regulator to provide power supply for the chip core?
For industry, people might choose this way to improve the supply noise performance. Any inputs?
At sampling phase, C1 samples the input charge, during the charge distribution phase, C1 and C2 share the sampled charge. Vout/Vin = C1/(C1+C2).
You can also do the charge conservation at node X and Y to get this. Let's say the analog ground is 0 (during sampling phase, X, Y and output are...
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