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?Instantiating verilog module in VHDL is like instantiating any other VHDL entity. you have to follow VHDL rules like width/type matching. because VHDL will not expand/truncate and signal unlike verilog.Also verilog module must be compiled in the library before compiling VHDL.In VHDL compilation...
problem in xilinx ise
i am using xilinx ise 7.1 .i have a problem , whenever i open 1 of my project xilinx doesnot open . all other projects are opening . why this problem is coming and what is the solution. will i have to make some new project or is there any patch for it..
failed to open data file
this is the code . 1 thing here that code was working fine to me previously but now its not working . i wanted to know is there a problem in s/w shud i reinstall it ..
module readfile;
reg [7:0] memory[0:7];
integer i;
initial
begin
$readmemb("data.dat"...
failed to open readmem file
I want to read a data file and take the data in memory,
while using following
$readmemb("data.dat", memory); (memory is a register array)
modelsim giving following error
** Warning: (vsim-7) Failed to open readmem file "data.dat" in read mode.
and it is not...
I am using xilinx ISE tool. In spartan3 library module like AND2,OR2 etc are available. when I used this module and instantiate them , in floorplanner it is showing only input/output buffer. and no other hardware.While when we write some behavioral code like assign c=a&b , in this case...
Re: Difference between inferring instantiating design elemen
Hi,
Thanks. Now I am clear about that. When we write code for some block its inferring and when we use the already available module its instantiating.but i have a doubt still in mind when you are inferring , the same available...
hi all,
I am using xilinx ISE tool for my design. I want to use the library elements available .However when i went through the help. for some elements i found that they are inferred not instantiated.What is the basic difference between these 2. plz help
thanks in advance
This is a very simple behavioral code for 8 bit input data:remember n bit data can be at most shifted by n bits.so you need log2(N) bits in shift control.
module barrelshift(a,b,sh);
parameter N=8;
parameter shift=3; /*equal to log2(N)*/
input [N-1:0] a;
output [N-1:0] b;
input [shift:0] sh...
DSP in VHDL??
The book "Digital Signal Processing with field programmable gate arrays" by Meyer gives some introduction to filter design with vhdl.Somebody must have uploaded it .
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