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Not-annotated nets,Primetime power analysis
Hi all,
During my power analysis i get some not annotated nets.
Summary:
Total number of nets = 588
Number of annotated nets = 540 (91.84%)
How can i check which nets are not annotated in my design?
Maybe this problem can be fixed if you generate the saif file with design compiler.Generate first the vcd file with Modelsim and then convert it to saif file with design compiler.
Hello,
1)can someone please explain what is the X-transition power that i see in the power report?
2)Also i get that Total Power= 5.045e-05 (100.00%) and i know that
Power-specific unit information :
Voltage Units = 1 V
Capacitance Units = 1 pf
Time Units = 1 ns
Dynamic...
It's my first ASIC design so i did not know this rule!Well i can do it,but i would not like to add more area/power consumption!
However,i think i do not have a choise here !
I would like to not get a glitch at the output of my combinational cell,because this cell output is connected with the output of my main design.
In fact i do not know if it does matter.This circuit is an interconnect and the output is going to be connected with a memory,my problem is i do not...
Well i understand this,but here is my problem:
i have a cell that has inputs A and B that are connected with FlipFlop1 and FlipFlop2 respectively. When these inputs do not change the same time i observe an output glitch.
The only reason that they do not change the same time is if FF1 goes from...
Hello,
i am doing a post-synthesis vhdl netlist simulation and here is the problem i observe:
I observe that the flip flop that change from 1 to 0 change faster than the flip flops that change from 0 to 1.The first ones change i.e. at 200 ps after clock edge and the second ones at 300 ps after...
Hello guys,
here is my problem:
I have some input ports that are connected directly with pins(group A) and some output ports that are connected directly with pins(group B).The fact that they are connected directly i can see it in my post-synthesis gate-level vhdl netlist.I was expecting by...
That is the problem,i do not think that i target any Altera libraries.The only library that i target is the technology library "fsd0a_a_generiic_core" of my design!I cannot understand why this message occurs..
This is the command i use vsim -L fsd0a_a_generiic_core -sdftyp...
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
Well,i dont use FPGA i used Synopsys Design Compiler of ASIS to get the vhld gate-level netilist, that's why i think this is not necessairy.I think these precompiled models concern FPGA designs..
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
yes i have read them,
http://quartushelp.altera.com/15.0/mergedProjects/eda/simulation/modelsim/eda_pro_msim_timing_sim.htm
These are the steps but it does not refer any primitive libarry.Also my SDF file is...
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
Yes i have seen this,but i do not understand where can i find this primitive library that i need?
Re: FATAL ERROR while loading design // ** Fatal: SDF files require Altera primitive
This is what i type : "vsim -sdftyp /instance/=C:/Users/designs/my_design.sdf work.my_design_tb"
Should i command this instead "vsim -L work -sdftyp /instance/=C:/Users/designs/my_design.sdf...
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