Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I´m trying to send a rectangular signal from DAC converter wich is connected to FPGA card. but i´m new in this type of design language.
so, i must create a function in VHDL of the rectangular signal in order to connect it to the pins of dac converter.
so i need some help. I´m interested in...
Hi,
I´m trying to interface a DAC converter in VHDL,in order to send a pulse, but i´m new in this type of design language.
so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.
thank you
the behavioral model simulation with xilinx works perfectly , but when i do post place & route simulation i get in quotient and remainder 0000000 :|
i think i have a problem with the clock maybe i should use a clock divider but in which frequence ?
Hello
I wrote a code in vhdl for a divisor of positive integers (eg 80:7 = 11, remainder = 3). my problem lies in the implementation of this code on FPGA spartan xc3s200 (freq = 50 MHz) to display the result on the 8 LEDs of the FPGA card.
My divider circuit consists of a dividend (7 bits) and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
