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Recent content by doham

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    Uart with parity check

    Can you configure putty using the opposite parity? Or make a HDL block that generates UART signal with wrong parity and loop it into your receiver block. Or simulate?
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    Altera Cyclone II BOard

    oh,... you WERE serious... okay.:oops: BTW, we have this on-going project: https://code.google.com/p/cubicboard/ A co-worker of mines had Linux (uclinux?) running on NIOSII on CycloneV. Anyone interested please let me know.
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    Altera Cyclone II BOard

    'directly' ? LOL... While you're at it, add virtualization so to run full win7 OS too. ;-)
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    Altera Cyclone II BOard

    You can't 'read text file' directly from FPGA. How about instantiating a M10K memory block and initialize it with MIF?
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    Silabs 2104 USB UART controller operating at out-of-spec 25Mbps

    Hi! yeah, we considered using SW USB sniffer to dump USB packets at SW driver level (which I has not ever done); but I'd imagine decoding the packet to find UART content could be difficult. I also used this RealTerm (realterm.sourceforge.net) to programatically sent data, but it still has...
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    Silabs 2104 USB UART controller operating at out-of-spec 25Mbps

    No, not really. The RX line should have the ASCII code of whatever sent from putty; its de-serialized value is cumulated in the rxbyte register (bottom right). I'm saying 'so' because when I sent multiple bytes from host computer (sent a file), I really had to zoom out to see 2 bursts of...
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    Silabs 2104 USB UART controller operating at out-of-spec 25Mbps

    Hi! I'm playing with the Silab 2104: The chip is hooked up to an FPGA via gpio. The USB end to connected to a windows machine running, of course the 2104 USB windows driver and putty. I was able to configure putty to use the USB com port at 40,000,000 baud 8N1 ( yes, 40 Mbaud!) And FPGA...

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