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Hi,
I'm trying to install Synopsys VCS (MX) on an Ubuntu 64 bit server (version 14.04).
Once VCS is installed and bash variables (licence, PATH, VCS_HOME) has been set, when i try to compile a simple verilog test file i get:
$ vcs test.v -full64
Warning-[LNX_OS_VERUN] Unsupported Linux...
Hi,
I've got a digital input, and according to that digital input I would like to generate a defined current (have a node where the current is set according to a predifined value chosen by my digital input). The order of magnitude of the desired current is 100nA/10nA (exactly 0->0.13uA...
Hi,
Actually the problem was that in the library the transistors are defined as subckt not mosfet model...
So I add to do something like:
Xm clk dd 0 0 n105 w=.. l=.. m=..
Hi,
I'm trying to use Synopsys 32/28nm Interoperable PDK. There is an HSPICE MOS definition in it (n105/p105) and I'm trying to use it.
So, as in the documentation, I'm doing:
*** test***
.lib '/.../SAED32_28_iPDK/hspice/saed32nm.lib' TT *line given in the doc (changed the path)...
.tran...
My problem is that I have an analog circuit (in the form of an HSPICE netlist) that monitors some parameters of my digital circuit (in my case the drop in the supply current caused by the computation of the digital circuit). I made a SPICE simulation with some simple digital circuits, but now I...
Hi,
I'm looking for a way to convert a Behavorial description (in VHDL or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys.
I've tried to look into Design Compiler / Nanosim but I couldn't find anyway...
Hi,
I have an (H)SPICE script which compute the energy consumed by my circuit for a different set of parameters through the TRANS SWEEP statement:
.tran 0.1p 600n SWEEP data=info
I would like to see how the energy vary for each set of parameter while doing a monte carlo analysis. That is...
Hi,
In (H)SPICE, I have a block of logic gates which requires a 16 bit input and have one bit output which is activated when the computation in the logic block is finished.
I want to feed the logic block with a set of input vectors (originally they are in a file with one 16 bit number for...
Re: Current drawn from supply with SPICE
I'm answering to myself as I progressed a bit but still don't have the answer.
When looking more carefully to the voltage of my output, I saw that somehow i get a small negative voltage in my output:
I guess this small drop makes my current rises...
Hi,
You can measure the Integral of the current drawn from the source and then multiply it by your supply voltage. Be careful on the timestep of your simulation, it affects the results.
Cheers
Hi,
First, I apologize if I post that thread in the wrong section of the forum, but my question is 2/3 analog 1/3 digital.
I'm making a simple simulation in (H)SPICE of a 1 bit full adder. I'm a bit curious about the current drawn from the supply of my full adder: the current drawn when my...
Hi,
I'm trying to learn how to use HSPICE through some tutorials and the reference manual but I'm running into a problem that I can't solve.
I want to know how my circuit responds for various input voltages through time:
.tran 0.01p Tsimu SWEEP vdd 0.15 0.85 0.10
However, I want to get...
Hi,
I'm trying to find a reference for computing or getting a (not so) gross value for the standard deviation for effective channel length (to perform a monte carlo analysis on my circuit). Despite looking for, I couldn't find anything except it probably follows a law of the type A/sqrt(M*W*L)...
Ok thank you.
So if i get it right, if i put an inverter after my CMOS circuit, the equivalent conductance will be C=Cp+Cn, with Cp=Eo*Er*Lp*Wp/Tox and the same for Cn.
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