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HI All,
I have a need to create a verilog-A model for a diode which serves the following purpose.
Referring to attachment:
Need to measure the current I(DP,DN) i.e. the leakage current through a diode (in RB mode) and measure the cap associated with netA.Then multiply the obtained I and C with...
I tried the same thing with 10K reistors also but it was taking some current from output of difference amplifier so i thought that may be due to output current flow from opmap, the nmos of the opmap output is going to linear region resulting in 10mV output DC.
So i checked with 100M but in this...
Hi All,
I was trying to design a difference amplifier to get a difference of two differential signals, say V1 and V2.
I intentionally used large resistors just to isolate the issue of resistive loading(which otherwise result in loss of opamp gain) but still i am unable to get the difference of...
Hi ,everyone i am trying to design a low voltage BGR.I am using 90nm Technology with 1v supply and vref is 700mV.Eventhough,I am getting variation of around 8mV across corners(SS,NN,SF,FS,FF) but vref curve is inverted parabola(i.e. U)(vref v/s temp).I am not able to figure out what may be the...
How to design a minimum size inverter?I am not getting any clear idea on how should i decide the minimum width for the nmos device on the basis of which i will design my pmos to nmos ratio for eual rise and fall time.And how to decide the maximum frequency of operation for this inverter.
I newly...
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