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Is there a particular reason you want to use an actual LFSR? I know that is how its done in hardware but the communication toolbox has a block for Walsh codes in the sequence generators section. If all you care about is simulation there should be no reason not to use this block. As for...
I have a question concerning phase synchronization for QPSK signals. I am having a hard time finding information specifically on how you synchronize a quadrature signal. Meaning I have found a ton of resources on how you can use a PLL to lock onto a sinwave but if you have both a sin and cosine...
Do you have the communications Toolbox? If so there are plenty of resources for generating spreading codes in there. Part of my masters project is simulating a CDMA system. If you want I can send you some basic simulink models.
Re: what is ISI channel?
An ISI channel is, as the name implies, a channel that causes Inter Symbol Interference (ISI). I am not sure if people use the term ISI channel to much but instead usually refer to a frequency selective channel that causes ISI.
A frequency selective channel is when...
Thank you for your replay but I am not 100% sure what you mean. I am still new to ADS so that may be why. Do you mean that I should place the part manually in the layout first then generate the schematic? I know you can do this in ADS but it seems kind of rediculous that i would need to do it...
I am having a issue assigning artwork to a sot23 bjt in agilent ads. The BJT is a SOT-23 package and I use the fixed SOT-23 artwork from ADS to assign the part but it is not properaly mapping between the schematic and the layout. The parts that are suppose to be attached to the base are attached...
I am having a really frustrating problem with the integrate and dump block from the communication toolbox concerning the sample times. What I am trying to do is simulate a communication system that has a integrate and dump block on the receiver and also a filter from the signal processing...
Thank you very much for your replay my problem was when i generated the fileter in matlab is used the wrong sampling frequecny.... for some reason i though that it wouldn't matter....
I am having a major problem getting the FIR core to work in my design. Here is what I have done so far. I have created a design which contrains a cordic which generates a sine and cosine wave and I am able to change the frequency of these wave over a wide range of frequencies. I have also...
hmmm that didn't seem to work. I even regenerator the ngc file and cleaned up my project file and verfied that the command line command was added into the compile chain correctly but it didn't seem to do much.
Thank you for your reply though
I am having an issue with creating and using a Xilinx core I generator using the core generator. My issue is when I add a core to my project (this case a cordic core) and I attempt to implement my design I get an error in the translate process that is shown below:
ERROR:NgdBuild:604 - logical...
By snap you mean under options->prefrences->grid display->pointer snap to grip needs to be checker right? It is on mine and I am still getting this error. Is there anything else you may have done to fix this?
I am not sure if this is the correct seciton of to post this in and it is my first post to please execuse me if its not. Anyways, I have a questions about LVDS. I am making a board that willl attach to an FPGA kit I have that has a paralell DAC on in which the inputs to the DAC are LVDS. My...
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