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Recent content by dineshprasad

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    problem in "Timing report" gerated by cadence

    hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . Other End Arrival Time 0.00 - External Delay 1.50 + Phase Shift 10.00 = Required Time 8.50 - Arrival Time 1.31 = Slack Time...
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    problem in understanding "Timing report" gerated b

    hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . Other End Arrival Time 0.00 - External Delay 1.50 + Phase Shift 10.00 = Required Time 8.50 - Arrival Time 1.31 = Slack Time...
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    Need help in TIMING REPORT generated by cadance buildgates

    hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . I have an idea , but i am not really clear about this. Other End Arrival Time 0.00 - External Delay 1.50 +...
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    How to code a mathematical set equations using verilog

    Thanks a lot........ it seems to be working.... dp
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    How to code a mathematical set equations using verilog

    hi yes "intersection" , but the result should be a set which has no's in set a, but not in set b. I have not coded that in any other language till now, is there any pre defined function for this similar operations in verilog HDL Thanks a lot dp
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    How to code a mathematical set equations using verilog

    hi , The example set may be 2 signals a and b let a={4,7} which means (4,5,6,7} (the set are continues and sequential series} b ={5,9} which is expanded as {5,6,7,8,9) a union b , should give a signal(out) c={5,7} which means {5,6,7} Thanks dp
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    How to code a mathematical set equations using verilog

    verilog code for mathematical hi, I have to compare 2 mathematical sets( set has no's) and have to get 2 different results 1. The intersection of tehe 2 sets 2. The Union of the 2 set. Can any one please guide me to how to code this in verilog HDL. Thanks a lot in advance dp
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