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Recent content by diablo1222

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    What are the difference between ASIC Verifation and Test?

    The target of verification is detect the bug of function. The test is find the fault of manufacture.
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    What is the most error of tape-out?

    If your design is full digital , the most error maybe is timing error. But if your design is mix-singal design, it is function error.
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    How does STA work for latch based designs

    Timing analysis of latch design is difficult. Over a large design, timing analysis becomes impossible. In the past, latch-based designs have been popular, especially for some processor designs. Multi-phase, non-overlapping clocks were used to clock the various pipeline stages. Latches were...
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    How to define High fanout net in Primetime

    high fanout net For prelayout sta, you can use command set_disable_timing.
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    Failure of register generation after DC synthesis

    The reason maybe as below: 1) The input of register is float 2) The output of register isn't connected to output( directly or indirectly) You can check the log file of synthesis to find the information about this issue.
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    Failure of register generation after DC synthesis

    Would you post your rtl code?
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    about future of ASIC design engineer

    The digital design isn't difficult to study, so I worry the furture. But for RF and analog , it is better than digital.
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    a question about dft in design compiler

    We add the MUX at RTL code, control by scan mode.
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    Handling of high fan out nets

    For high fanout net, such as reset, it is needed to handle separately. After CTS, you need route the high fanout net before routing rest logic.
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    Why is that IO pads operate at higher voltage than core?

    For digital I/O, it include the lever convert function.
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    Using CVS when designing HDL code

    CVS and HDL code We use the CVS for version control. It is a pool to store the file. But we use other solution to manage the project.
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    Timing mismatch between SDF and RSPF

    The rspf represents RC delay in terms of a pi model(2C's and 1 R). The accuracy of this model is better than sdf format.
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    Max Frequency acheivable using 0.18u technology

    If use standard cell, it can work at 600 Mhz for simply design (tsmc 0.18).
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    How can I find all the negedge trigged flip-flops.

    Yes, you can use the design compiler. After read the desig and map, you can generate the report.
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