Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There is a variable in most decks that set the tolerance
---The Default setting for property check is 0%. Users should check with IP/Design providers for proper tolerance.
Do a search for "tolerance" in your rule file and it should tell you how to set the default from 0% to a higher value.
Hi,
I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place.
dac_out is defined as a digital output
This is simply 1 or 0 based on:
------
module DAC (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, DAC...
Not that I'm aware of, do you have both schematic and GDS and you want to find the location of the different blocks or are you going in with just the GDS and hoping to extract schematic information ?
well first point is its always better to have an even fold, this will have matching better (I know its not important in an inverter, just good practice, if you needed to increase the strength or add in dummy devices)
Yes, sounds like you want a LEF or ABSTRACT view
This is used by digital designers to show pin placements and overall size of the physical design for place and route. also used for IP blocks as an initial delivery to a customer during IP development.
Let me know if you help with this.
Hi saber67,
That’s a very open ended question. But I’d say as a starting point you can decide what current you want passing through the transistor and what overdive voltage is required (Vgs – Vt) --- where Vgs is the gate-source voltage and Vt is the threshold voltage.
Use the equation
IDS =...
The only base layer dummy are diffusion and poly.
I was just pointing out effects with layers other than metal in my last comment. Didn't mean to imply the NWELL was also a dummy layer required.
Yes, I suppose my thinking was better matching because the cascode could be embedded in the layout of the current sources. Results in bigger area but a little more robust for density and matching. I just wasnt 100% sure why the smaller L is a requirement, thanks for the answer.
Yes, on point 1. On a basic level the density checks are to ensure an even spread of metal and to ensure all required metal is formed correctly.
On point 2, the need is also present for the base layers because these also have effect on device performance. Some effects can be
- Well proximity...
Hi,
Normally when I look at a PMOS current mirror with cascode they are sized with different lengths. As an example the PMOS current source could be 7.5u/3u (W/L) and the cascode set at 7.5/0.35.
During layout then it requires two seperate regions for the PMOS sources and cascode region...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
