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Re: Post Layout Simulation
You must do it!!
Generally, parasitic component of Metal line (ex. Cap. Resistor) is not defined
in a library. In analog circuit, the parasitic make additional capacitor, resistor
(influence bandwidth and bias, crosstalk...).
The post simulation result might be...
hspice option
Hey guys.. I want to know how to save node voltage value which only I need.
Although I don't need voltage value of almost nodes, HSPICE save voltage value
of all node. So silmulation is loose..
I think, if it is possible, simulation will be done more quickly.
Do you have...
Re: single stage amplifier
I think they are used to make something like OPAMP, BIAS Circuit,
Differential AMP... not to be used by themselves, usually.
For example, Beta multiplier is consist of CS with Source degeneration..
And Diferential Amp has 2 CS amps.
cascode amp has CS and CG...
Re: layout
R = (sheet resistance) * (number of squares)
but at a corner, resistance is a little different.
I guess ur design rule document, from foundry, mention about sheet resistance of each metal layer.
good luck..
Re: 10 or 100
You can use 10uA source and than use five times large current mirror transistor. You will get 50uA.
It can be a little different because of some side effects.
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