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Recent content by dfgt

  1. D

    I need help in systemverilog

    I am using Zybo, I assign "SI" to write to a button, when I press it, all the data is filled the same, it does not give me time to collect one data and another. So, once I press "SI" the DIR led turns off and the "DOR" led turns on and the "SO" button reads only one data. How can I Improve my...
  2. D

    Help needed in System verilog

    I saw a FIFO example here, and once I was trying to synthesize it didn't work. I took out the "assign", I removed the "always" and "begin" and it works, but now I have another problem. I am using a button to write data, but I think the clock is too fast, since it should be 16 data that I can...
  3. D

    Help needed in System verilog

    module fifito( input logic clk, input logic MR, //RESET input logic [3:0]D, //DATA IN input logic SO,//read input logic SI, //write // input logic TSC, output logic [3:0]Q, // DATA OUT output logic DIR,//Empty output logic...
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