Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

devas

Recent content by devas

D
Signal prdata cannot be synthesized, bad synchronous description.

Hi, Remove the "end if" below the line "pr_data <= (others => '0'); as shown below: READ_REGISTER_PROCESS : process(clk) begin if (clk'event and clk = '1') then if reset = '1' then prdata <= (others => '0'); else case paddr(8 downto 2) is when...
- devas
- Post #2
- Oct 27, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
problem with test*bench verilog at models*im

Hi, When compiling your code with Modelsim I get 2 errors about signal sel. Remember Verilog is case sensitive! After changing this I do not get any compile error in the part you posted above. Devas
- devas
- Post #4
- Oct 27, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Looking for library declaration of IP Module

Hi, The use-statement given does not point necessary to a package declaration. It points only to a library hwicap_v5_00_a which maybe has only entity/architecture declarations in it. A use statement pointing to a package declaration has the form: use <library>.<package>.<suffix> Your use...
- devas
- Post #2
- Oct 25, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Xilinx synthesis and PNR flow

Hi Beowulf, Your schematic looks fine to me. I do not know the output file of promgen. I have never used it. I am not aware of a Xilinx document with such a schematic. Even it makes sense for every designer. Devas
- devas
- Post #5
- Oct 25, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Verilog Question about Always sensitivity list

Hi, always(*) is Verilog-2001 syntax. It simplifies the sensitivity list. * means be sensitive changes on any values which are read in the following group. Devas
- devas
- Post #2
- Oct 17, 2010
- Forum: ASIC Design Methodologies and Tools (Digital)
D
[SOLVED] verilog and vhdl in same project, problems

Hi, When your simulator/synthesizer has mixed language support there is no need for XHDL. Devas
- devas
- Post #4
- Oct 11, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Xilinx synthesis and PNR flow

Hi, A starting point: - Xilinx Synthesis: XST User Guide (UG627) - Command Line Syntax/Tools: Command Line Tools User Guide (UG628) Devas
- devas
- Post #2
- Oct 11, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
[SOLVED] verilog and vhdl in same project, problems

Hi, You can mix VHDL and Verilog if your simulator and synthesizer supports both languages (is sometimes an add-on feature). In your Verilog code instantiate your VHDL ip-core just like if it was a Verilog module. Devas
- devas
- Post #2
- Oct 11, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
How to start implementing transmitter and receiver on fpga using VHDL or verilog

Hi, Open a text editor and start typing: VHDL: "library ieee; ...." Verilog: "module transmitter(...."
- devas
- Post #3
- Sep 29, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Help regarding error in ise synthesis

Hi, Line 52: contains a generate statement. A generate statement must have a static (fixed) condition. You use a signal "stepsize" in this condition. A signal is not a static. Change the signal in a constant (static) and this error will be fixed. The same applies for the other generate...
- devas
- Post #2
- Sep 29, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
[SOLVED] xilinx core generator

Hi, CoreGenerator is part of the Xilinx ISE software. You can download it from the Xilinx website. The webpack version is free and includes also CoreGenerator. Devas
- devas
- Post #2
- Sep 27, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
problem in initialization

Hi, I have done a quick simulation with your uart code and in my simulator n_reg will be '0' after reset. From your simulation picture I can not see how long the reset pulse is and how it behaves compared to the clock. Maybe you can post your testbench code also so I can use it with my...
- devas
- Post #2
- Sep 27, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Quartus Ver 4.2 & Nios 3.2 shell - Compiling error !!!!

Re: Quartus Ver 4.2 & Nios 3.2 shell - Compiling error ! Hi, You use a very old Quartus version. I do not believe that version is supported on Windows Vista. Devas
- devas
- Post #2
- Aug 9, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
help with reading a hex file in vhdl

Hi Haneet, Something like: library ieee; use ieee.std_logic_textio.all; library std; use std.textio.all; architecture xxxx of yyyy is file fin : text open read_mode is "<path to your hex file>"; process(zzzz) variable rdline : line variable hex : std_logic_vector(3 downto 0); begin while not...
- devas
- Post #5
- Aug 5, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
help with reading a hex file in vhdl

Hi, The package std_logic_textio has functions (HREAD) to read hex values from a file. Devas
- devas
- Post #2
- Aug 4, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

devas

Welcome to EDAboard.com

Recent content by devas

Signal prdata cannot be synthesized, bad synchronous description.

problem with testbench verilog at modelsim

Looking for library declaration of IP Module

Xilinx synthesis and PNR flow

Verilog Question about Always sensitivity list

[SOLVED] verilog and vhdl in same project, problems

Xilinx synthesis and PNR flow

[SOLVED] verilog and vhdl in same project, problems

How to start implementing transmitter and receiver on fpga using VHDL or verilog

Help regarding error in ise synthesis

[SOLVED] xilinx core generator

problem in initialization

Quartus Ver 4.2 & Nios 3.2 shell - Compiling error !!!!

help with reading a hex file in vhdl

help with reading a hex file in vhdl

Part and Inventory Search

Connect with us

Online statistics

Forum statistics