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After tapeout
need to do max-product test
first need write a task to generate vector file (0101.....)
then need some tools transfer this vector file suit for test format
(now I use software : atpc)
Q1. What is atpc , is this populer for Design house? , is this a standard for test machine...
fwrite in verilog
module tb;
integer os1;
initial
begin
os1 = $fopen("E:\\tb.txt");
//$fwrite(os1,"aaaaaaaaaaaa");
//$fclose(os1);
end
always
begin
$fwrite(os1,"aaaaaaaaaaaa");
end
endmodule
//-------------------
Best regards,
Davy
Hi
I am a new guy for IC design
and want to learn ARM
so pls somebody tell me
how to setup the ARM self-learning enviroment ?
Can use Altera Startix to try ?
what kind HW I need ?
what kind SW I need ?
thanks in advance!!
verilog generate pulse
I think it's no way to create a pulse in degital ckt,
(use a faster clock is not a pulse)
I think you need a hard-macro
(Delay cell, use spice to calculate the delay to meet your pulse width)
then in verilog:
wire pulse,pulsed,pulse_want;
dly(.out(pulsed), .in(pulse))...
generate sdf for pt
Q1 How to use DC to generate .sdf from .db(come from Foundry)
if use "write_sdb -output top.sdf"
==> DC show error message ( -outpur only support by PT)
Q2 Need and constrain when generate SDF?????
After DC Synthesis
use VCS compile gate netlist to generate fsdb
VCS hold on after run 1ms
( cannot run to $finish written by pattern)
the fsdb file size never increase
press ctrl+c
use Verdi to trace waveform cannot find any problem
( just see the clock stoped , but dont know why)
then use...
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