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I agree with you, that with this small amount of current is hard to achieve the goal.
I didn't get what you mean with "the zero phase may be the power hog."
Can you provide me a better explanation?
Thank you.
Kindest Regards
Thank you,
is the topology that I have already implemented but without clk, in my case is continuous time comparison. Will something change if a clock is added?
Kindest Regards
You should care about the load that you will drive and the frequency you need.
You need to have a short propagation delay in respect to your clock signal period. If you read the slides I posted you, you will see that the delay mainly depends on the load(in your case the load is represented by...
Dear all,
I'm searching a comparator topology suitable to work with a maximum total budget current of 100nA.
As the current budget is really low, I was wondering if it exist a topology that allows me to obtain a short delay time.
The maximum tolerable delay has to be 1us, with an over...
Thank you FvM, as I suspected there is no other ways to flip the voltage across the cap without the use of an inductor. I was thinking something similar to a gyrator, but as i know it cannot store energy, then is not feasible.
Thank you erikl, but I forgot to specify that the cap. is inside a device. The voltage flip has to be done externally. Actually I implemented out a second cap. which is charged with opposite voltage. When the DPDT switches, the charges are shared, and half voltage(circa) drop appears on the...
Hello everyone,
I would like to ask you if there is a way to flip the voltage across a capacitor without the use of an inductance in parallel.
I know that connecting an inductance in parallel with a capacitor, will make the system oscillate, and after half of period of their resonance...
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