Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all
I am quite new to ASIC design. This time I want to design a circuit to delay for a certain time, such as 3us. I would like to use inverters and capacitors.
My current ideas is just tweak the L and W and the value of the capacitor. And maybe using two stages are better (easy to layout)...
Hey,
I think this Power Network Analysis is done after Power Network Synthesis, which means that ICC's already generated the relevant two files "pna_output/strap_end.VDD.vpad" and "pna_output/strap_end.VSS.vpad".
The path "pna_output/" is the generated path after PNS.
In your case, during...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
