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Thank you for your reply.
Yeah, you are right. In the LSB comparison, the comparator input parasitic cap may be comparable with unit cap. But if it's maintained below, let's assume, 1 unit cap. I think, it should be OK for the resolution. In this case, we may assume input parasitic cap=4.8f...
Hi,
I think the cap in the summing node had better consider all DAC array cap. In the 10-bit 50Ms/s case, the cap in one branch is 2^10=1024*unit=4.9p, which should be much larger than one comparator input transistor parasitic cap.
Hope this is helpful.
Thanks
Daniel
The vco problem has been solved, just due to the stop list in the configuration. Symbol or verilogams should be chosen , not spectre. But the resisitor one still can't run. with the error message.
Fatal error found by spectre in `worklib+test_res+vams+0x10000001', during
circuit...
Dear adhil:
I remember ic5141 has this feature. If not modify the .cdsinit or copy all the files in the $CDS_INST_DIR/tools/dfII/sample/local to $CDS_INST_DIR/tools//dfII/local and change the name of cdsinit to .cdsinit
Hope helpful
Daniel
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What's more, I found the sourcecode of the example in The Designer's Guide Community - The Designers Guide to Verilog-AMS.
Listing 22. sinusoidal voltage-controlled oscillator
Surprise. Five files included. How can I use them?
If just run run-me in terminal, it would say" can't find the file...
After reading the chapter 3 and chapter 4 in this excellent book, I want to simulate some examples. However, I can't make them work on my computer . For example, the VCO in chapter 3,
(1) I make a new cellview with verilogAmsText type, then fill it with the VCO code and make a symbol.
(2) After...
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