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Recent content by daisyzari

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    VHDL code to a logic circuit

    I did checkk the RTL of the code but I can't seem to understand it along with the code. It seems to be some sort of clock divider to another code but I don't how it works as a clock divider for that code. Can you please explain to us how the code works thank you very much.
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    VHDL code to a logic circuit

    I'm having difficulty understanding this part of code that I've been using in my I2C project. gen_clken: process(clk, nReset) begin if (nReset = '0') then cnt <= (others => '0'); clk_en <= '1'; --'0'; elsif (clk'event and clk = '1') then if (cnt = 0) then clk_en <= '1'; cnt <= clk_cnt; --...
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    I2C VHDL reading from slave

    no.. the above code is the complete code.. :D
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    I2C VHDL reading from slave

    We were able to write a data to our slave which is an EEPROM atmel 24C04 but we can't seem to read from it. Please help Thank You.. :smile: This is our code -- -- -- State machine for reading data from EEPROM -- -- Testsystem for i2c controller -- -- library ieee; use...
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    question on i2c: reading slave acknowledge and sent data

    I have a question on making a master I2C. I don't know if it has been asked before, but how can i get the acknowledgement of the slave that happens every ninth pulse of the scl? Should I just assume that it did acknowledge and assert that ack_in on my vhdl code is 0 (which means the slave indeed...
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    question about states and stuff?

    **broken link removed** -- Simple I2C controller -- -- 1) No multimaster -- 2) No slave mode -- 3) No fifo's -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -- library ieee; use...
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    Question on something?

    Thank you..
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    Question on something?

    -- -- -- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.i2c.all; entity DS1621_interface is port ( clk : in std_logic; nReset : in std_logic; Dout : out...
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    Question on how to do this? Image inside

    Thank you.
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    Question on how to do this? Image inside

    **broken link removed** I just want to ask how to indent the source under another like in the image.. Thanks..:smile:
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    Another question on OpenCore's I2C Controller Core code

    Thank you! :-)
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    Another question on OpenCore's I2C Controller Core code

    constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; constant CMD_START : std_logic_vector(2 downto 0) := "010"; constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; constant CMD_READ : std_logic_vector(2 downto 0) := "100"; constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"...
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    another question on opencore's I2C core controller

    We would just want to ask the need of the hookup of the signals from the package to the signals of the interface. This is the code package I2C is component simple_i2c is port ( clk : in std_logic; ena : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(7 downto 0); -- 4x SCL --...
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    A beginner's question

    Thank you everyone it has become more clear to us now.
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    A beginner's question

    Can someone help me understand what this code means? constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8); Thank you :-D
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