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I suppose the max_tran limit is coming from the values specified in the .lib. So even though the output load looks small, you need to check what is the max value specified in the lib and perhaps your load exceeds this one, hence the violation.
(a) These views are typically in the form of .lib files which are loaded through the .synopsys_pt.setup files. Hence for each corner, you should have a .lib characterized at those PVT conditions and specified in your link_library to get loaded into Primetime for analysis in that corner.
(b) The...
Switching activity file also known as SAIF in short, is a file that captures the toggling activity of all the circuit nodes in the design. It is similar to the VCD, except that this is normally much smaller in size and hence easy to generate (takes less time) and manage (less disk space). It can...
half cycle path
a path where the data is launched by a FF on posedge of a clock and captured by a FF on negedge, hence the time available is only half a cycle instead of full cycle where both FF are working on posedge
Typically what is done is a single PLL is used to output the highest frequency required by the digital and all other required frequencies are generated from the PLL output using clock divider circuitry. Hence a big SoC may have only 1 or 2 PLLs depending on the requirements and the rest are...
Power Analysis in DC
Hi,
For this you need to load a VCD. The VCD will have the information of toggling activity at all nodes including clock gates and thus calculates the power more accurately.
Else, I suppose you can do a set_case_analysis on the clock gate input to make it '0' and then...
If I understand correctly, "clk" is the top level port on the netlist which is connected to IO pin PAD of the IOCELL and the C pin is an output of the IOCELL going to the entire design. Thus the path is clk->PAD->C->core.
In this case, defining the RootPin as clk should be ok, but I didn't...
Power Analysis in DC
To get leakage power, the .lib you use must have the leakage power information in it. DC will sum the leakage power numbers of all the cells used in the design to produce the final leakage power number. As for dynamic, in Step 4, since you have not defined any clocks, the...
help regarding synthesis
@amraldo: Yes, the synthesis tool will implement the logic as specified in RTL with whatever cells it has in the library. The tool does not alter the logic/functionality. If you run an equivalence check between the RTL and synthesized netlist, it will and should pass.
False Path
another possible false path is the path to the input of any synchronizers. For eg if u r using a 2 FF reset synchronizer to synchronize the deassertion of the reset in ur design, then the async path to the reset pin of the synchronizer FF can be set to false. Only paths from the...
Grouping Clocks
If you are putting both the clocks into a ClkGroup that means you want to balance these two clocks. That in turn means you want the clock skew between 2 endpoints within clock1 or between clock1 and clock2 to be as similar as possible. This is what the tool is trying to do here...
design compiler
The switch -boundary_optimization (compile -boundary_optimization) will result in optimization across hierarchies. Make sure u don't include it in case u want to prevent it.
Clock Latency
The correct definition is Def 2. especially in the context of STA. However, you are right, sometime people do refer to Def 1 when trying to describe latency of the circuit .. I would say this is not really clock latency, but latency of the design -> how many cycles from pumping...
gate level netlist site:www.edaboard.com
Also check for floating nets. Best thing would be to go through all the Errors and Warnings in the synthesis log file and fix all of them. The fewer the unfixed warnings, the more robust is the netlist you pass on to backend.
-D
STA and CTS do not have the same goals. As the names suggest - STA is a timing 'Analysis' step, where we do an analysis using tools such as Primetime to check if the design meets the timing specification. CTS on the other hand is a clock tree 'Synthesis' step - it is a step in the Implementation...
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