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Recent content by cysco

  1. C

    Do SDF gate simulation check the false pth setting in the timing constraint(.pt file)

    Someone said that the SDF gate simulation will check the false path is correctly setting in the timing constraint(.pt). But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So...
  2. C

    How to Writing this statment in VHDL

    In verilog, I can write like this: assign next_lookup = lookup[15:0] & {16{lookup_en}} // lookup_en is 1 bit. How to have the same statement in VHDL??
  3. C

    what's difference between spirit, eclipse and core-assembly?

    up
  4. C

    what's difference between spirit, eclipse and core-assembly?

    They all are the tools for IP integration?
  5. C

    Tail pipeline registers - how they fix the timing issue

    Re: Tail pipeline registers But I see someone said: When DFTmax scan compression is used, compression block can produce excessive toggling on scan output pads. To prevent this, clocked output shall be used (tail registers). Do you agree.
  6. C

    Why high fanout of test clock will result in IR drop issue?

    whats ir So can you explain why high fanout of test clock will result in IR drop issue?
  7. C

    Why high fanout of test clock will result in IR drop issue?

    ir drop Why high fanout of test clock will result in IR drop issue? Thanks in advance.
  8. C

    Tail pipeline registers - how they fix the timing issue

    Tail pipeline registers How do these registers fix the timing issue when using adaptive scan? Thanks.
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