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Recent content by curious_engineer

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    Is it common to route using inner layer wires?

    thank you. What do you mean by spacing to drill holes? Why would that requirement be different from any other layer?
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    Is it common to route using inner layer wires?

    Beginner question... I have a 6-layer board of which 1 is a GND layer, and 3 are split-pwr layers. In areas where there are no power connections, can I use those inner power layers for routing other connections? I ask this because it's much easier to do so because the top and bottom layers are...
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    Rewiring a via connection

    Thanks a lot. Thats the optimal soluition. I just realized that I can simply pop up the pin of the chip and manually connect that to the appropriate top layer pin (which is DC voltage, so I can just use an extra power supply). THis is a crude way compared to your neater one, but it is easier...
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    Rewiring a via connection

    Hey guys, I have a problem. A particular via on the physical board is connected to layer 2, but that connection is wrong, and I need to wire it to another pin on the board on the top layer. How can I make this connection without shorting layer 2 and the the top layer pin? In other words, I...
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    Any way to plot Oscillation frequency vs Time in Cadence?

    Re: Any way to plot Oscillation frequency vs Time in Cadence One month later, reviving this topic because I have come back to this project. The "freq" command works, but it does not seem very precise for some reason. I can't really observe overshooting, and it does not start at 0. I would...
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    Unexplainable DRC clearance errors

    Thank you so much. Problem solved. I never messed with net classes...I guess the designer of the first board may have changed some settings.
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    Unexplainable DRC clearance errors

    That fixed the majority of the errors. Thanks. Still have the routing clearance errors remaining. I'm already using minimum wire width (0.008 in) so I assume they are not centered correctly because of some grid issue. Appreciate the help guys.
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    Unexplainable DRC clearance errors

    I did change the grid values a few times during routing/placing parts. However, that would not explain the DRC errors that involve only the vias of the package (the errors that are independent of routing), right? Thanks.
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    Unexplainable DRC clearance errors

    Hi, yes it is the same DRC file used for both layouts. Here are the contents of that .dru (it's for a 6-layer board): layerSetup = (1+2*3+4*5+16) mtCopper = 0.0178mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.0356mm...
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    Unexplainable DRC clearance errors

    I am getting clearance DRC errors on a part in layout (a 68pin package), some of which are independent of my routing (the vias in the package design are too close apparently), as shown in the image below. I am also getting routing clearance errors. The reason why this is unexplainable as far...
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    Any way to plot Oscillation frequency vs Time in Cadence?

    I have an oscillator, whose behavior with respect to time I want to observe. For example, I want to be able to see how long it takes before the oscillator starts oscillating at a desired frequency, if there is any overshoot, if the frequency somehow changes over time, etc. I cannot figure out a...
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    Question on amplifier topology for 1.2V supply

    I am having trouble deciding the architecture for an amp to be used as an integrator for a sigma-delta ADC. The supply is 1.2V. Does this rule out folded cascode? My idea was to make it one-stage in order to reduce the number of poles, but I don't know if its feasible w/ the limited supply...
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    Simulating a DAC in Cadence

    haha, that was a silly mistake. Thanks.
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    Simulating a DAC in Cadence

    I will look into the strobing. Thanks. I will also try using your code. This is the code I had before (testing w/ just 1us intervals for 3us): out = outfile("<data_out text file> "w") selectResults(`tran) for(x 1 3 time = x*0.000001 - 1*0.000001 fprintf(out "%5.3f " time)...
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    Simulating a DAC in Cadence

    you're right, I could have just done that. Thanks. Anyways, now I am wondering how I can easily extract Vout data at each relevant time increment to capture the output voltage for each input combination. So say I want to record the output value at every 48us, store the values to a table, and...
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