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Re: soc encounter geometry check -short errors in VDD VSS
In encounter , I have not deal with PG pin or PG net, but I know all of the IO PAD have the PG pin, why they (except the VDD and VSS IO PAD) have not short errors ?
but I will try your method, Thanks!
hi, my clock(HCLK_PAD) of desgin is input from a input PAD(PISW), when I reprot_timing -delay max, there are some violation path that the clock PAD contribute the most delay time, follow is one violation path:
(My clock period is 100ns ,but for the clock input PAD is 349.62 , so it's very...
Hi, when I add iofillers ,using the geometry check in soc encounter, there are some short errors in 1.8v VDD pad and VSS pad. and the error show that there are short between this pads and adjacent filler cells, I checked in the Virtuoso and find nothing unnormal, So why ? please help me,thanks!
hi ,I want to ask what's the differnece between encounter verify geometry and calibre DRC, I know we must pass the DRC before tapout , so can we say if the DRC has passed, the verify geometry is unnecessary in soc encounter?
digital asic design flow
hi we are desiging a small digital system that include a cpu ,and two IPs with AHB bus, i am a little confused about the design flow:some one said i should synthesis the whole design in the DC , and some one told me that i should partition my design in the SOC...
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