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Recent content by Cluny

  1. C

    how to connect two lines outside the cell?

    @JoannesPaulus: Thanks a lot, It works with the "JoinNets" Function. But I still have a rule error concerning the bulk connectors. It seems that only the contacts connected with the right net are recognized and those on the left side, connected with the other gnd net are ignored... in...
  2. C

    how to connect two lines outside the cell?

    Hi, I have a sublayout cell in with two "gnd" lines which are not electrical connected by a another metal-line. I want to have only one gnd-pin for this cell and I want to connect the lines at the toplevel. the "gnd"-Pin is located at the first line, the second has only the name "gnd"...
  3. C

    how to reduce mismatch of latch comparator?

    Since I have a lot of comparators working together on one chip, this method seems to be very comfortable. Furthermore it's rather a cancellation algorithm than an additional circuitry.
  4. C

    how to reduce mismatch of latch comparator?

    I've found a good solution for my problem: I couldn't expect that I can totally decrease the mismatch-effect. But that's not necessary. The mismatch by the layout or whatever leads to an Input-Offset which I'm cancelling now by an additional external circuit. The decision-threshold is just...
  5. C

    how to reduce mismatch of latch comparator?

    Hi, I've been designing a class-ab latch comparator. This comparator hast to compare a minimal differential input signals of 1mV with the speed of at least 100 MHz. The common problems occurring with latch comparators like offset-voltage, kickback-noise and so on... are not a problem...
  6. C

    spectre rf - dynamic resistor value?

    Hi, I need a simple resistor for my circuit but this resistor has to modulate another circuit. So I must not use a static resistor value. Instead of this I want to have a value described by maybe a function. Or maybe a kind of behavior description... if (v_in < v_treshold) res = 20 else...
  7. C

    large signal input matching

    Yes, I have a Class-C power amplifier and I want to match the input for high power level... I've found a solution... using psp simulation for different input power, especially input power level at maximum output power.
  8. C

    large signal input matching

    Hi, I want to do the input matching for a power amplifier. In addition there's a dynamic load at the output which change its value over the input power range. Thus, there's definitive a non-linear behaviour and I'm not sure for which "drive point" I should do sp simulation? Do you have to...
  9. C

    problem with load pull simulation

    load pull simulation Hello, I'm designing a power amplifier and I tried a Load-Pull-Simulation in Cadence... as it is explained in this application note http://www.cdnusers.org/community/virtuoso/resources/SpectreRF_PA533AN.pdf My Question: To obtain the optimum load for maximum output power...
  10. C

    need help... doherty amplifier and power combining

    doherty amplifier + 2009 I have to design a full integrated doherty power amplifier at 5GHz. After designing the carrier in Class AB and the peak in Class C I tried to connect each other at the outputs (the inputs are still not connected)... but I'm not able to get the same current-phases for a...
  11. C

    breakdown voltage vs. voltage supply

    I'm sorry about the confussion. Power amplifier means only that I'm using a simple common emitter topology for creating a power amplifier. - My problem seems to be that I cannot handle with these different breakdown voltages. VCEO = 2.2V VCBO = 7.7V (similar to VCES???) VEBO = 3.0V Actually I...
  12. C

    breakdown voltage vs. voltage supply

    Hello everyone, I need some help with my (first) power amplifier. the bipolartransistor I'm using for has a breakdown-voltage Vceo = 2.2V and my supervisor told my that I have to use 3.3V voltage supply. So my question is... is it really possible to use this configuration? I mean you have maybe...
  13. C

    Verilog: question with blocking assignment

    Hi dcreddy1980, I don't really know why your result would be 3??? There are blocking assignments in the always block, which are successively executed. I suppose that this leads to the right and desired result. min = min_out // min = 4 if (value[0] < min) // right, 2 < 4 min =...
  14. C

    Verilog: question with blocking assignment

    Thanks for the hints. The real program I've written is more complex than my simple example has shown. I want to get the minimum of a lot of values and want to take two values and check them at once (in one cycle). The calculated min_out is the new minimum which I have to compare with the next...
  15. C

    Verilog: question with blocking assignment

    Hi, I want to calculate the minimum of two values compared to an older minimum value. And I want to do this in one cycle. In my calculation I take the first value and compare it with the old minimum value. Then I take the new (maybe) minimum value and compare it with the second element. I...
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