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I am not sure that you can do that. Maybe you can try putting a 0 volt voltages source between net1 and net2. Since you have declared net1 and net2 as globals then you should be able to put the voltage source anywhere .
1) p-mos has about have the drive strength that an n-mos does due to hole vs electron mobility. To get same fall/rise edge rate the p-mos has to be 2x the nmos.
2) A 2 stack series device is required to be 2x the size of just a single transistor.
3) A parallel device might have only one of the...
Re: CMOS or PMOS
The majority carrier for a NMOS are electrons and holes for a PMOS. Electrons move about 2x faster than holes so NMOS have more drive per capacitance. To get the same drive strength of a NMOS the PMOS has to be 2x bigger than the NMOS causing the circuit to see more load due...
The best bet would be 4x loading. 3x loading is what some text say based off some equation solving for the optimal loading of cmos cells. The answer turns out to be ~2.8 but this is without including internal parasitic loading. 4x turns out to be closer to the optimal.
Added after 11...
Re: question in CMOS
As the input goes from vss to vdd or vdd to vss, one stack turns off and one stack turns on. Before one turns on and the other shuts off there is a period of time when both are on.
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