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any papers on this structure?
Added after 12 minutes:
Khong-Meng Tham and Krishnaswamy Nagaraj "A Low Supply Voltage High PSRR Voltage Reference in CMOS Process" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 5, MAY 1995
choosing probe all will do save all the node but not save verilog module internel node.
and also, save all will generate a huge file that exceed 2G for my simulation.
pnoise noise type
In pnoise anaylsis window, there are four items in the noise type select at the bottom: Jitter, modulated, sources, timedomain. select Jitter, after running the PSS and pnoise simulation, the jitter value can be calculated directly.
I design a all digial PLL, but i don't know how to make sure it is a stable system.
do you have any suggestion, or introduce me some reference books?
thanks
sigma delta pll mit
I simulate the Sigma Delta modulator in Verilog, It produce a time-b(t) table. then it is included into the Hspice netlist file, using a behavior counter, the whole fractional PLL can be simulated within one day.
This may be the most accurate,while not very time consuming...
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