Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi all,
anyone could help me to explain these items, "ius,irun,ncsim,gcc"?
in my eyes, ius is a cadence software,
irun is a command to run simulation,
ncsim also is a command to run simulation,
gcc is a tool to compile c file,
and am i right?
what the difference between irun and ncsim?
and i...
yes...i have also seen set_clock_uncertainty in the sdc file...
so...the clock margin and clock uncertainty have nearly the same function in our sdc file?
but, the clock margin is used in both setup &hold timing(for it does not point to setup or hold seperately), for clock_uncertainty, u can...
hi vijayR15,
thank you...
and i have seen an example: clock period=15ns, and in the constrain file, it will set clock_margin=0.85(15% margin), and the actual clock period used in the design is:15ns*0.85=12.75ns, so it is over-constrain,just like you said.
"The value for the...
hi all,
i want to ask a simple question,
why should we set clock margin in constrain file when systhesis?
and the typical value of the margin should be ?
thanks all...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
