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Recent content by chiranjeevinaidu

  1. C

    meet error when insert filler cell

    helo , I dont know about ICC , I know cadence EDI , we have one command like refinePlace -preserverouting true (it's refine the overlaps cells ,without touching the previous nets ) can you try similar type command in ICC also....
  2. C

    effect of voltage scaling on set-up and hold times

    if any cell varies depends upon pvt conditions.below once 1.process 2.voltage 3.temperature for example: if the cell voltage 0.9v ,cell delay: 0.02ps these values are taken as ruff values, if cell voltage is decreased to 0.87 ,then delay of cell is increased.becaz transition time of cell take...
  3. C

    Unable to load Calibre DRC report in Encounter

    Hi do the below command loadViolationReport -type Calibre -filename *.rve file
  4. C

    Why normal buffers don't have equal rise and fall times compared to clock buffers?

    Hi, clock buffers having drive strength is more compare to normal buffers.and it's having doping concentration is also high....... so high drive strength buffers having equal rise and fall times.....tr and tf
  5. C

    consider 2 nmos connected in series

    what abt inputs ? is it tied to high or low..?
  6. C

    [SOLVED] Doubt Regarding Timing Sanity Check

    Hi, before your going to Place and Route ...do the sanity checks zero wire load model we do the timing also we do reg2reg is positive or some margin.... and it's not more than 200ps or 500ps ,it' depend upon the top level timing margin
  7. C

    what is skew number?

    HI ...> skew is calculated between the two flops.these are two types 1.positive skew 2.negative skew ... > after CTS (clock tree synthesis) is done.then only you come up with skew number.. Clock.report
  8. C

    Increasing Yield of a chip.

    HI Kashfi Israr I have shared below points it's my experienced .... case1:using default cut vias probability of chips failure is exits.why because between two layers connect with single via .so via is not connected properly,so chip is malfunctioning....... case2: using multi cut vias...
  9. C

    IR Drop and EM with SOC Encounter

    if you want run IR drop must should be following input files are required 1.power pin locations of both VCC and GND (VCC.pp) (GND.pp) 2.bump files/bump lef 3. cl files of macros/std.cells and technololgy files 4.sdc (for twf file)
  10. C

    setup and hold time of lockup latch

    Hi deepen, mainly lockup latches are used 1..lockup latches necessary to avoid skew problem during shift case of scan based testing case1 :if launch flop and capture flop sitting for away.( physical design view ) ..> it necessary to met skew two different clock domains case2...
  11. C

    IR Drop and EM with SOC Encounter

    Hi early power analysis before your are going ran IR drop and EM in vstrom tool from cadence 1..In you design where the std.cells are placed close to each other or logic is placed only one side of core area,it causes IR drop issue 2..where you have seen long net ,it causes EM migration issue...
  12. C

    What does Constant hierarchical Pin(s) means in RTL compiler?

    Hi constant hierarchical pins are either connecting to zero or one.... In synthesized net list those hierarchical pins are connecting to tie Low or tie High ... (1'b0) (1'b1)
  13. C

    why to use multiple lockup latches and how?

    Hi lockup latches are used scan based design for hold timing closure of shift modes. where clock skew is large and meeting the hold timing is big challenge due to uncommon path,that is why lockup latches are used to connect two flops in scan chain having excessive clock skews/uncommon clock...
  14. C

    Increasing Yield of a chip.

    HI , ..> using multi cut vias to increse yield ..> there should not be a electro migration problem Regards chiranjeevi
  15. C

    setup and hold time of lockup latch

    HI deepen, Basically lockup latches are used scan based design. 1.two different clock domains > Positive or negative level latch?? It depends on the path you are inserting a lockup latch. Since, lockup latches are inserted for hold timing; these are not needed where the path starts at a...
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