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Recent content by cherjier

  1. C

    fpga project hardware and software

    Hi Hydragon, Feel free to contact me for discussion. cherjier@gmail.com
  2. C

    Recommended android phone for embedded developers

    I would recommend you go for NEXUS series which should support all the latest android version.
  3. C

    Which memory to choose for CPLDs

    CPLD do not need external flash to store it image only FPGA need external flash.
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    How to change clock frequency of Xilinx XSA 3S1000 Board?

    Hi, You can just use a DCM to divide your 100Mhz by 4 to get the 25Mhz clock. thank you.
  5. C

    Gas Detection system using wireless sensor network implemented in FPGA board

    I think you will probably interfacing with sensor and a gsm module which usually interface using uart and audio input/output. For the sensor, you might need to see if the sensor output is dc or ac voltage. If ac, you might consider an adc if you need accurate reading from the sensor. For the...
  6. C

    Gas Detection system using wireless sensor network implemented in FPGA board

    hi, i guess you need to clearly know what you want your FPGA to perform, how many sensor/data it handle and how you want your FPGA interface with all your sensor and how you want to process your data. All FPGA like Altera and Xilinx they do come with Soft processor so you can design standalone...
  7. C

    MII to AXI4 interface

    if i'm not mistaken, my understanding from your post is that you are trying to build a bridge for AXI to MII so that you can directly connect the UDP/IP stack from open core to your PHY directly which is your point 2. I don't think it is possible as the MAC layer does quiet a number of tasks...
  8. C

    1000Base-T propagation delay

    Hi am85, Usually those information need to come from the manufacturer. they can estimate the delay for TX and RX base on simulation of their PHY design. Here is an example report that Vitesse release their PHY delay...
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    MII to AXI4 interface

    Hi, MII is a standard interface between the PHY later and the MAC layer. AXI4 is usually for processor and peripheral interface. So basically you can't direct convert AXI to MII. you need the MAC later integrated in your system, which the link you post is a MAC controller.
  10. C

    image display in verilog using FPGA

    hi, depend on the interface of your LCD, HDMI, DVI or VGA. the simplest 1 would be VGA.
  11. C

    Freelance FPGA designer needed

    Hi, I had a lot of fgpa design experience and currently working in a fpga company. I can help you on the project. Feel free to contact me at cherjier@Gmail.com
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    1000Base-X Auto Negotiation Doubt

    1000base-x auto negotiation Hi All, I have a question regarding auto negotiation for device A and device B. Here is the process for dev A and dev B: 1. both device Start link timer and start sending /C/D0.0/D0.0/ 2. both device Link timer done and start sending /C/dev ability reg/ 3. after...
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    Reg I2C Bus - should I expect Z as input in place of 1?

    Re: Reg I2C Bus u cab output a Z instead of 1 or you specify to select open drain for your i/o standard. In that case, u will need the external pull up resistor for I2C
  14. C

    How to use SRL16 primitive in my verilog program

    simulate srl16 sorry for the delay, hope it's not too late for you. this is just the basic script file. you can just change the path to your own directory and double click the test.bat
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    How to use SRL16 primitive in my verilog program

    how to use verilog primitive i guess you did not compile the xilinx library in modelsim. you need to compile all the verilog library before it can be used in modelsim. you can use "vlog" to compile the library. if not sure about the GUI, if you use script, you can upload it here so that we can...
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