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Recent content by chenmy

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    OPAMP-RC continuous-time filter

    Hello,everyone!When designing a fully differential OPAMP-RC continuous-time low-pass filter, the CMFB bandwidth should be made larger than the OPAMP's unit-gain-bandwidth or smaller than it? why?
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    How to determine needed GBW and DC gain of the LDO from spec?

    qslzaio,hello!The closed loop GBW can be caculated from the time you want Vout to settle to a certain value within some settling error,for ex, 1%.Just like the way in which we design the OTA's GBW in ADC design.
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    Op Amp Design - Hand Calc Questions

    "I tried to derive these on my own by writing the large signal Id (saturation) equations, and keeping the constrains (Vds versus Vgs-Vt) satisfied; is this the right approach?" This approach is not necessary. The easy way is just to remember, for analog design ,each MOS must be in saturation...
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    Performance of the SHA

    Hi!If you are using a pipeline or cyclic ADC structure,the noise performance of the S/H is the most important to the overall ADC noise performance.that means the KT/C noise as well as the OPAMP noise must be less than the ADC quantization noise.
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    'Analysis and Design of Current-Commutating CMOS Mixers'help

    current commutate mixer could any one who has the paper 'Analysis and Design of Current-Commutating CMOS Mixers' By Emmanouil T. Terrovitis UC berkeley Ph.D. Dissertations ,2001 share the paper with me?thanks a lot!! chenmy
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    design spec of LDO regulator?

    Dear All: A simple question about LDO:what do you think should be the design spec for the LDO's current load?max value or the average value? (I wish to use an LDO for digital power supply(1.0V).In the normal working condition, the max current value for digital power supply is about 2mA ,while...
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    How to improve PSR of the bandgap?

    Re: PSR of bandgap I think another important point to take care is : If the OPAMP and the bandgap share the same power supply,Make sure the OPAMP's PSR do not degrade the bandgap's PSR. Best regards! chenmy
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    question on low drop out regulator

    Hi,Leonken: For NMOS , Vin is the supply of OPAMP,so Vin >VG>Vout+VTN should be met. so VDS=Vin-Vout>VTN (about ~700mV in 0.35um process) For PMOS,you only need to make VSD=Vin-Vout larger than Vdsat(usually about 100mV~300mV) So the PMOS LDO headroom is larger than NMOS LDO. It is the NMOS...
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    How to deal with the sweep of Kvco on PLL system design?

    kvco curve lineage050505, you can use .measure statement in Hspice to measure the period and then the frequency of the VCO after .tran simulation. Best regards! chenmy
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    Power Noise in Analog Chips

    Hi,neoflash: From the design perspective, First,you can run ac simulation and see the PSR from VDD to VCTRL of VCO (the chargepump should be turned off,and the loop filter and VCO should be added) you should make the PSR less than -90dB @ frequency larger than the PLL bandwidth. Also,you...
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    How to deal with the sweep of Kvco on PLL system design?

    what do you mean by vco has a linear tuning curve Hi,Salem: First of all,I think there is no problem of your simulated result. But, in practice,Kvcomax:Kvcomin=10:1 is definitly not a good choice.It will cause the PLL bandwith to vary 10x.What is more,If you run full process corner...
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    a problems of analysing the PLL phase noise with PSS+PNOISE

    qpss vco phase noise simulation Hi, I have tried the 2nd method with Cadence 4.55 and here is the report: I did it for 4 times with different numbers of harmonic in PSS of 400,120,80,40 I specify the 'tstab' as 1u, which is long enough for my PLL to be stable.Please See The Figure below. I...
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    a problems of analysing the PLL phase noise with PSS+PNOISE

    pnoise ideal switch Hi,gunturikishore,I am really thankful to u because u have helped me a lot! And I think we are now standing very close to the truth. ur analysis of my circuit is right .The only thing I should point is that before the charege pump there is a phase frequency detector. I...
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    a problems of analysing the PLL phase noise with PSS+PNOISE

    pnoise relatve harmonic gunturikishore,I know that u suggest me put 2 sources :one is the 50MHz input, the other is 2GHz LO,and then set Beat Frequency to 50MHz and do PSS. My confusion is that the PLL does not need 2GHz LO to work .What the PLL needs is only the 50MHz input and it will...
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    a problems of analysing the PLL phase noise with PSS+PNOISE

    pnoise absolute sweep OKay! gunturikishore,let me tell u my flow in more detail: Setp 1: use DC source as the input reference Step2: set PSS 'Beat Frequency' to 2 GHz and Choose 'Oscillation' and the output voltage is the VCO Diferential output .Also,I set the 'Tstab' long enough...
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