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Recent content by chandru4u4

  1. C

    when the "signal will update" in fpga

    thanks for reply ...my main doubt is ,In the process-1 rising edge after i will do some operation after that only i am using "addr " ..at the same time i will update the "addr" content in another process-2, so it will affect or not ....in detail below .. initi...addr<=0; -----Process-1------...
  2. C

    when the "signal will update" in fpga

    hello every one... I am working in xilinx ...artix 15t fpga . In this i need to know , in below two process what value will there in "addr" varible in first rising edge ....kindly reply any one ...both clk is same initi...addr<=0; -----Process-1------ rising edge of clk temp<=ram(addr)...
  3. C

    need help for" Recall the last state"

    thank you for replying , could you please send me correct coding for jk flip flop
  4. C

    need help for" Recall the last state"

    Hello everyone , i am new with vhdl design , i design a one jk flip flop program . here how can initialize "no change" condition . library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library...
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