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PhD , pipeline 10-bits ? Sampling rate > 100 MSPS ? CMOS ?
digital calibration you use ? I study now it.
0.5LSB error may too much, INL wants less, 1/4LSB error (static+dynamic) , you agree ?
Matlab tried, looks good only 1/4LSB .
typical values of vdsat in nmos
any CMOS technology...
Saturation in subthr is ~125mV , Vdsat ~150mV is moderate inversion, Vgs-Vth ~ 200mV for this Vdsat. Run simulation see this you clear.
vdsat for 0.18 um technology
vdsat 150mV ok, large gm for current Id. vdsat 50mV is weak inversion, model is not good.
weak inversion good for very low power, low speed.
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