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Recent content by carleethian

  1. C

    Initialize Lookup Table Verilog

    I'm under the impression that a initial block won't synthesize in Verilog... What I've done is that I'm using a for loop to calculate the values for the lookup table during reset. Just like Dave said, the compiler seems to run through the for loop and store all the values in memory. Thus...
  2. C

    Initialize Lookup Table Verilog

    Hi Dave, so is there not a way to get this to work in Verilog? The only way I've initialized memory is in reset, am I correct that if I put something like that for loop inside my reset statement inside my always block, that because it's creating constant expressions it won't synthesize into...
  3. C

    Initialize Lookup Table Verilog

    So that won't create a divider in hardware? I'm trying to avoid the divider and do all of my multiplies & divides before compilation.
  4. C

    Parameterized Generated Case Statement?

    Yes, it needs to be synthesizable. I'm essentially creating a lookup table. I've decided that using an array and initializing that array using directives or something like that would be optimal... I essentially want to create an array and then initialize each value in the array by using it's...
  5. C

    Initialize Lookup Table Verilog

    I want to create a lookup table inside an array. The code below won't compile, can someone please let me know what I'm doing wrong? Does the for loop need to be in the always block? What I really want is for the compiler to do all the math and load the values into memory... localparam...
  6. C

    Parameterized Generated Case Statement?

    So... I guess there's nothing that exists in Verilog to generate a bunch of statements in the pre-compiler? Is it possible to put a generate or for loop inside an always block at all?
  7. C

    Parameterized Generated Case Statement?

    Hi guys, I want to create something like the following, essentially creating a lookup table based on the number of states and max/min that I set outside the generate loop. Can I do this without any problems? parameter STATES = 4; parameter MAX = 5; parameter MIN = 1; case(r_STATE) genvar...
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