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you need an fsm to keep track of when you have encountered hc="00".
when state=not_encountered
if(HC="00") then
increment<='1';
next_state<=encountered;
else
increment<='0';
next_state<=not_encountered;
end if;
when...
I have one global clk signal in my design, no gated clocks or clock assignments.
@ Fvm:
indeed you were right. In the simulation model I found
-- Register delay
CONSTANT C_TCQ : time := 100 ps;
and
qspo_int <= spo_int after C_TCQ;
So the delay comes from there. Thanks for your help
Not a problem exactly... it introduces glitches because my brams don't have such a delay so the two memories are a bit off-sync. Synchronous multipliers and other components also propagate this delay (although somehow they do the right computations even though their inputs are a little screwed...
Hello everyone!
I'm having a problem with the behavioral simulation of a single port distributed ram component in isim. It appears that the output of the ram is not clock accurate, but comes 100ps after the clk rising edge . The thing that confuses me is that the output is registered...
I'm...
I tried using modelsim XE but couldn't get it to work. In compilation, it says that starter version doesn't support 2 HDLs. I use VHDL but I think an ipcore I use from coregen is written in verilog, so I'm stuck with Isim for now. Luckily I have managed to overcome the last flip flop problem. I...
Again I am witnessing a very strange and VERY annoying flip flop behavior...Take a look at the diagram and tell me how is that behavior even remotely possible under ANY circumstances
**broken link removed**
I am using the gated clock flip flop vipinlal suggested. Note that if I change the flip...
Still I get a problem. D propagates to Q instantly. Is there a way to ALWAYS make sure that a register propagates d to q with a delay of 1 cycle? Why does it propagate instantly?
E.g:
WrEn is always '1'
D changes every rising clock edge
I want D to propagate to Q the next cycle. If WrEn ever...
Actually this is a very small part of a much bigger circuit implementing the tomasulo algorithm. Wren is created by an fsm (driven by the same common clock as everything really) and some logic so I expect it to come a little after the rising clock edge. Does behavioral simulation take into...
Hello,
I'm stumbling on this register behavior on my project.
**broken link removed**
The code for the register is this
architecture Behavioral of regn is
begin
process(Clk)
begin
if(Clk'EVENT and Clk='1' and WrEn='1') then
Q<=D;
end if;
end process;
end Behavioral;
The rising clock...
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