Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by butxarakham.nh2008

  1. B

    SoC tool to connect IP core?

    Hi everybody, I have some problem when build a SoC with MIPS IP core. If I have netlist file or Verilog file of IPs from vendor, what tools will connect these IPs in SoC (such as SoPC builder of Altera)? or I must connect them by hand.? I read some documents on Internet, CoreAssembler of...
  2. B

    SoC with MIPS core - which bus it use?

    hi all, i got a issue that in the one SoC with MIPS IP core, which bus will MIPS connect with another IP ? Plz help me. Thanks so much.
  3. B

    Looking for materials about optimize timing a design using Verilog code

    Hi everybody, i have project about optimize timing the design on verilog code, but i can not find any documents of this topic. Remember that only on RTL code such as you use paralell coding style... , not by comment line such as "optimize_ timing....".... Anyone help me? Thanks all,
See more

Part and Inventory Search

Back
Top