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Hi all,
I use ncverilog to simulate & usually debug from ncsim cmdline. Its obvious that the tool can check all the object path names (for example when we dump wave it can check path name validity) but I cant find any tcl command that help me list all instance path names (a kind of object...
E is the only one?
So anyone here used E in an NC tool ? How does it work ? So we can compile & simulate design code (write in Verilog) & testbench code (write in E) in the same tool at the same time ?
Thanks for any reply !
Thanks all for your replies !
Hi aji_vlsi, thanks for your detailed & helpful reply.
I've found some info about IUS, its lately version support almost all basic & strong features of SV which can improve our Verification performance.
However there're also many possitive comment about...
vcs/questa for systemverilog
Hi all, I have some questions really need your helps :
I've heard of Cadence tool named IUS. It seems to strongly support SystemVerilog. Anyone here tried this tool please share your experiences ...
1. Does it support all features & constructs of SystemVerilog ...
I have compared the running time between Verilog 5.5 & Verilog 3.4 in both RTL & GATE levels. And the result is Verilog 5.5 work much slower (nearly 3 times). Even when System Verilog pack is not included.
The new version ofcourse has more features and so more libs added. But running that slow...
OK, I finally installed NC Verilog 5.5 and the result is most of my old testcase Gate-Level stucked in this new version with this type of ERROR :
ncelab: *internal* (static_merge_roots - non multi
event to munti event not good!).
Anyone has some experience with this ? Plz help !!!
If you really love ASIC Field (that's what I feel), so ... nothing is so hard & nothing is boring :)
Me ? Maybe becouse I works with network protocols most of the time :( while I want something more "art" like speech recognization or image processing or mp3 or sumthin else ... :D Maybe coz my...
I know I'll receive another warning by this thank-post. But I have to say the doc is very helpful to me. It's exacly what I'm looking for ! Thanks a lot, aji_vlsi !!!
testbench using verilog tasks .pdf
Hi all, I have a short question :
How to call a tcl task inside testbench ? I created tcl lib & I can call it from cmdline (interactive mode) but it seems not able to call these task inside testbench (Like PLI system task).
Is there any way ? (I'm using Verilog)
First off, I'm sure you that you can easily move to ASIC Filed if you used to be a software engineer (Especially if you familiar with Firmware, MicroP ...)
Programming for ASIC is not so far from works of a solfware engineer. You just need good tools to practice in the early days. Book is just...
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