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Recent content by brotherjam

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    problem when insert clock gating

    problem solved i wrote a test module yesterday, and synthesis it. report_timing, the path endpoint which is integrated clock-gating cell is reported as a "posedge clock flip-flop". I change to another target library, no timing violation. The endpoint is a "clock gating cell". I think the...
  2. B

    problem when insert clock gating

    I am sorry, but can you explain it a little? In clock gating, en just have setup&hold requirement of clk. I don't think DC has some error. So it should be my fault. How can I solve this problem?
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    problem when insert clock gating

    timing report just the same. CKcheckpin1: see below from solvnet. my icg is same as the figure Question: I modeled an integrated clock-gating "latch_posedge_postcontrol_obs" cell, as described in the Library Compiler User Guide: Methodology and Modeling Functionality in Technology...
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    problem when insert clock gating

    i use a integrated clock-gating cell in my design. but timing report seems to have some errors here is the timing report. clock gating cell TLATNTSCA. why use clkcpu'? i think setup check should be one cycle, use clkcpu, not clkcpu':?:?:?:?:?:? thank you very much Startpoint...
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    Please discuss Chip security

    Hi, everybody Please discuss "Chip security" such as Timing attack , Simple and Differential Power Analysis(DPA), Electromagnetic Analysis And how can we protect our chips. Thank you !
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    conditional assignment statement

    yes, you can do this like this. it is a mux followed a register.
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    to power and area,which is the best for the LUT,PLA,ROM,CAM?

    I think ROM may be the best choice for large data lookup. because ROM has fewer area and lower power.
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    how to make my design as black box

    i'm sorry that i just do the front-end design. in DC also the set_dont_touch can do
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    A question to DC(set_input_delay and set_clock_latency)

    set_input_delay dc the input delay of the first command is 2 related the source of the clk if you use the second command simultaneously. input_delay + clock_latency
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    How to do Scan Synthesis?

    you'd better to follow the toturial of the DFT,or give your error information
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    how to make my design as black box

    modue test (in1, in2,in3, out3); input in1, in2, in3; output out3; //synopsys black_box //(you can find it in DC manual) //synopsys translate_off assign out3 = in1 | in2 | in3; //synopsys translate_on endmodule
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