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Verdi error: include file "define1.vh" cannot be read "/y/yy/define2.vh", 1:"
when i use the filelist, including /x/xx/define1.vh, /y/yy/define2.vh, /z/zz/*.v...
but verdi print a lot of errors, such as "*Error* `include file "define1.vh" cannot be read
"/y/yy/define2.vh", 1:"
could anybody be...
ncsim dump fsdb problem
when I add
//////////////////////////////////////////////////////////////
initial begin
$fsdbDumpfile("./cosim.fsdb");
$fsdbDumpvars(0, top);
$fsdbDumpon;
#Length
$fsdbDumpoff;
$display("cosim success");
$finish;
end...
Re: ncxlmode help
i tried remove INCA_lib and re-run...still....problem
ncvlog: *F,DLNFS: Packed library for 'worklib' was either corrupt or the file system cache consistency check failed. To correct the problem, remove the packed library, and recompile. If the problem persists, contact...
ncxlmode help
when i am running ncxlmode in linux, some error happens:
ncvlog: *F,DLNFS: Packed library for 'worklib' was either corrupt or the file system cache consistency check failed. To correct the problem, remove the packed library, and recompile. If the problem persists, contact Cadence...
Bipolar vs CMOS?
Biploar process is more fast, and more power consuming.
COMS process is relatively slower, and less power consuming.
My question is which kind of design should use Biploar process? analog ? I/O ?
as I stated, in the read side, 4 data out of every 5 read clocks , like 0 1 2 3 x 0 1 2 3 x
in the write side, every write clock per data, like 0 1 2 3 0 1 2 3
accoring to the freq ratio, the duration of 4 data write is equal to 5 data read.
I don't think they are the same case.
The write clock is faster than read clock in your referred article.
But in my design, write clock is slower than read clock.
how to determine the depth of this FIFO?
write clock is 40Mhz, read clcok is 50Mhz
data is written into FIFO constantly and repeatly, like 0 1 2 3 0 1 2 3
data is read from FIFO repeatly, lie 0 1 2 3 x 0 1 2 3 x
x means no read.
that means every 4 write clock, data in and out of FIFO are the...
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