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What I mean to say is, everything is working in simulations but not when it is implemented on my Nexys 3 board. Nexys 3 board already has a microusb port on the board itself for UART communication. So all we have to do is connect the USB to microusb cable and assign assign that port as the...
1. The data given is decimal value 10. So the output - at least in the simulations - corroborate the given input.
2. We checked the baud rate multiple times - the calculation done to get the value, baud rate selected on the RealTerm software - and we didn't find any discrepancies there.
3. The...
Well we are designing it for only sending 1 byte as of data now. Also the code for UART Tx-Rx was given to us directly by our prof who is also using the same code
Also is there a way to generate the tx_wr one pulse again once tx_done has gone high ?
uart_tx is working only in simulations. Not...
I am trying to send a 1 byte of data from my Nexys 3 board to my PC using UART communication. But the problem is whenever I try to view the data on Real Term no matter my input(hard coded into the code or given via switches) the transmitted data always shows 0. I checked by simulating the entire...
I have the code for dividing two numbers but whenever the final result is a decimal number, I always get the floor value. I want my output to be such that if the final value (lets say X) is greater than or equal to X.5 then the final value should be X+1 else remain X. Is there a way to do that...
I want to find the time period of an unknown signal in microseconds. I already have a code that helps me find the frequency of an unknown signal. Is there a way to modify that code to find the time period of that signal in microseconds ?
`timescale 1ns / 1ps
module freq_counter( input...
My aim is to find the pulse width of an unknown incoming signal. To that I have written the following synthesizable verilog code but I am getting the warning XST 1710 and XST 1895. When I try to simulate the code, I get 'XXXXXX' in red.
Top module:
`timescale 1ns / 1ps
module top(...
I want to simulate the code for a seven segment display but I am not getting how to write the test bench for the same. I generate the test bench using ISE Xilinx but when I simulate by giving input values SEG and AN are shown XXXXXX(in red) in the simulation waveform.
Code:
module sseg(...
I am trying to build a Binary to BCD converter using the double dabble algorithm.
I wrote the code for the same and when I simulated the entire thing it was observed that my if statement is not getting executed properly.
`timescale 1ns / 1ps
module test_6( input [13:0] bin ...
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