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Thanks,
Is there a way one can obtain some hands on training in verification with HVL like Vera, systems verilog, system c, with self learning tutorials?
Hi,
I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers.
Thanks in advance
I have a rather simple question. Is there a vhdl code for the Microprocessor - FPGA interface.
I am writing data from a microprocessor to FPGA (into BRAM). I need a generic code for a interface between microprocessor and FPGA BRAM. I will be using Altera FPGA.
Thanks
It can mean either, the Design which is to be verified, or it may mean creating verification environment,i.e. writing behavioral models, and test pattern generation, so as to verify the DUT.
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