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Hi everyone
I'll use different Input Pad for SDATA and SCLK.
I think SCLK can be sampled with SDATA. because they have different delay time.
If you have any good idea, please let me know.
Thanks
billy
hi everyone~
I need your help.
I'm a newbie in the dc_shell, but I have question about set_input_delay.
rffe_slave or any other interface need to be initialized.
they said "please use SSC" signals that is data line.
rffe has only 2-wire.
generally SDATA generated from SCLK clock,
so I did...
hello everyone :)
I have question on verdi compiler.
Usually we use parameters with pre-processor keyword `define
I defined on tb_top.v like this,
`define TARGET_FPGA
`ifdef TARGET_FPGA
`define SBIT 8
`else
`define SBIT 6
and I used parameter on tb_sub.v that defined on tb_top like this...
The following is an example of the casex statement
is this code ambiguous? Thank you!
always @(*) begin
casex (SumMsbSat1[16:13])
4'b0000 : SumMsbSat3 = SumMsbSat1[13:0];
4'b1111 : SumMsbSat3 = SumMsbSat1[13:0];
4'b0xxx : SumMsbSat3 = {1'b0, {13{1'b1}}}...
Hi,
i have some problem on ncsim option.
i set the waveform dump to fsdb format,
$fsdbDumpfile("./sim_dump/ADC.fsdb");
irun // without -64bit
result : no problem
but,
irun -64bit
result :
ncelab: *W,MISSYST (./tb/tb_top.v,153|32): Unrecognized system task or function (did not match built-in...
hi, viju
I've never seen something like this code.
your code has 2 definition, 1 is parameter, 1 is interactive `define.
and u combined it.
how about change parameter to `define text1
and `ifdef text1 `define ONE1
and also there is no reason to define dual clock.
have a good day~ :)
hello everyone.
i have some problem to compare RTL vs xilinx netlist.
when i convert to netlist, there is some unexpected changing name on netlist.
anyone have an experience in this job?
BR. billylee
thanks a lot :)
I found good answer on this site such as
'A good paper to check out is "Complex Clocking Situations Using PrimeTime".
Just google that title.
'
and solvenet
Key word : set_clock_groups...
there are many clocks on my design
clk0 - clk50
so i want to set_false_path between all clocks
set clock_list [list clk0 clk1 .. clk50]
foreach each_clock1 $clock_list {
foreach each_clock2 $clock_list {
if { $each_clock1 != $each_clock2 } {
set_false_path -from...
hello ljxpjpjljx
thanks to your reply
but I'm wondering about linking skill for mixed structure not -sv option, -sv option is needless at this source code, sorry for your confusing :) but thanx a lot
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