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Recent content by billjoy

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    What is a ring FIFO and what's the benefit of using it?

    What is ring fifo ? any benefit about using ring fifo with gray code access in asynchronous design ? any paper can reference ?
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    [HELP] Vertuso .tf transer to astro .tf

    One syupid question how to trans candence vertuso .tf to astro .tf ?
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    About USB HOST 1.1 PHY

    Q1 : Why USB 1.1 PHY just is two PAD cell? Q2 : Where can find these PAD cell name ( T$MC0.13um) and datasheet?
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    What does ECO stand for ?

    Docs on ECO It seems no IEEE papers about ECO, I think as for tutorial :Try find verdi training course - nECO !
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    Please explain to me what is Ping-Pong FIFO?

    ping-pong fifo What i s Ping-Pong FIFO? Normally we use PING-PONG fifo under what situation? Any Document ? Is there any verilog RTL example(free )?
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    What is AMBA, why is it used and how does it differ from DMA?

    Q1.What is AMBA, Why ARM define AMBA , any documeny about the history of AMBA? Q2.Who is the father of ARM? any article / ebook about the history of ARM? Q3.Why most IP use AMBA, define M/S can get waht kind benefit for SOC design? Q4.If AMBA also define for bust RAM access, then what's...
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    [REQ] Encounter RTL Compiler !

    150 million gate-com? DC or RC? where can I find the document about the limit?
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    [REQ] Encounter RTL Compiler !

    Q1. What's the max gate number (limit) for DC(can handle ) and for RCC(can handle )? Q2. I start to use RC compiler(Encounter RTL Compiler ), anyone can share the RC compiler training material/tutorial (with lab is better)? tks in advance!
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    [HELP] NV-SIM Problem?

    setenv in verilog makefile Q1: In NC if ncvhdl ncverilog is ok but ncelab with error **broken link removed** Here is my run procesure /========== ncvhdl -work work ./fa.vhd ==> OK ncvlog -work work ./adder4.v ==> OK ncvhdl -work work ./testfixture.vhd ==>...
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    [HELP] ncvhdl/ncverilog how to?

    nc vhdl fsdb thanks to wadaye : but my problem is in my IC, some IP is VHDL some is verilog I need add my module and integrated those IP How to generate mix(vhdl+verilog) fsdb? I see so run_script use ncsim .... input dunp.tcl but I dont know TCL Is there any document for reference??
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    [HELP] ncvhdl/ncverilog how to?

    ncvhdl Question: How to generate fsdb in ncvhdl/ncverilog(v5.4)? pls give the detail commend (how to call novas/verdi pli?) under rethatlinux enviroment? tks in advance!
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    [HELP] Fermi-Dirac Fomula?

    How to derivation the Fermi-Dirac Formula in thermodynamics ? f(E)=1/(1+exp((E-Ef)/kT)) ?
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    [Help]Verilog Problem?

    Hi debussy1765 Would you pls give me a complete example I dont understand the statement wire [11:0]x=m[i][100:90]; would you pls explain more detail ?
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    [Help]Verilog Problem?

    here is the error message without +v2k argument //================= Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with +v2k to support this construct multidimensional select. "./model/aa.inc", 11 //================= with +v2k argument...
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    [Help]Verilog Problem?

    vcs invalid bounds count it's a simulation model, two dimension array can let simulate more convinence it's inside a task : //=========== reg [32:0]mem[127:0]; reg [127:0]databuf; task a; input output int i; begin i=0 @(.....) repeat(33) begin...
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