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How can i built the diffencial input signals (see attached pic for detailed info) by verilog-A? The time step and voltage step are both constant.
There are so many steps ,so i need a simple method.
Thanks in advance.
Sometimes， layout engineers try to save die size by putting trimming pad in scribe line . We paln to try this way in a new product.
Anyone know which product using this technology, and any other suggestions about this.
Thanks in advance！
No microcontroller internal.
I put a 10uF cap between vcc and gnd, no effect with output noise.
If i put this cap between output and gnd, the noise vpp increase obviously.
Only Smith trigger, inverter and buffer between input and output.
Added after 28 minutes:
Good news. I have found the...
Test issue description:
Input -3V~3V square waveform. The output signal should be inverted 0~3V signal.
But i see big noise added on the output signal.
The noise frequency is about 70KHz, and it is independent with input signal frequency.
So what is the main reason?
Thanks in advance.
Re: BW of analog switch
For a simplest T-gate, it can be equvalent to Fig1.
R1 is the paracitic resistance of the metal. The R2 is the on resistance of the T-gate. R2 is several times than R1.
C1 equals to C2, they are the paracitic cap of the cgs and cgd.
C3 is the paracitic cap between Drain...
Re: BW of analog switch
To FvM
Thanks for your reply.
Actually,i think we can simplify the model of T-type analog switch to only a low pass filter, which only includes a resistor and a cap.The resistor is the on resistance of the switch.And the cap is the equivalent cap of the output node.
We...
I designed an analog switch. The switch is T type, which is composed by 2 T-gate and a NMOS.
The PMOS W/L is about 35000um/0.5um and the NMOS is 7000um/0.5um. That means the on resistor is very low, the test results is about 2.5ohm; but the paracitic capacitor is very large.
The BW...
Thanks,echo47.
But is seemed to be useless.
I want to know how to realize two sin signals add together.
To throwaway18
I confused with that the low frequency output signal will infect high frequency signal, when the two sin signals add together by resistor.
to throwaway18
Yes, I know.
BUt i want to know How to add the two sinusoidal signals together.
Can you explain it to me or tell me where can i get the answer.
The buffer will consume quiescent current, and it will make circuit complex.
Thanks to you and tsanlee.
I just have change current source of erroramp from 0.4uA to 0.8uAto inprove line and load transient to meet spec.
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