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HI, it's an IC interview question, can anyone give me a perfect answer?
When your design's setup time is not enough, what will you do?
How to design a 5.5 frequency divder with some simple CMOS transistors?
my codes need to read a vector and I put the vector file in the codes folder, but when I compile it with VCS, it always told me:
How can I do to solve it?
Problem in using VCS
$vcs -debug -f file.v
if file.v is a verilog file list, you have to use '-f' to tell vcs you want to compile it instead to treat it as a verilog file.
booths algorithm example
Thanks uditkumar1983 and lever!
Hi, deepu_s_s, I am willing to share your design if it dosen't has any issue with IP sensitivity or confidential.
algoritm booth hardware
my problem is:
1. can anyone help to convert this VHDL to verilog2001?
2. how to design a parameterized Booth based multiplier with Wallace tree?
3. what is the performance of Booth multiplier compared with synopsys DW lib's
fscanf systemverilog
I do not use sv to process my text file; I just use it read the vector from the file and feed the vector to the testbenches or DUT.
The reason why I need a sv class here is the class can be easily reused and called.
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