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Recent content by bhaskarg

  1. B

    [Moved] begining arrival time

    dear all can any one explain 1.begining arrival time 2.other end arrival time in timing reports of hold violation generated by encounter cadence thanks in advance
  2. B

    dangling violations during addng power stripes in encounter

    hi all after desiging power stripes am getting dangling violations how to remove those violations. thanks in advance
  3. B

    how to fix hold and setup at gated andnon gated clock

    thanks HTA.... one more doubt what is the use of amobea view in the ENCOUNTER cadence thanks in advance
  4. B

    STA debugging commands for setup and hold .

    hi, am new to vlsi i hope this would help u to fix hold violation ecoAddRepeater -term {net name} -cell #buffer cell name # example: ecoAddRepeater -term {anna_clk_sync_reg[16]/D} -cell BUFFD2
  5. B

    how to fix hold and setup at gated andnon gated clock

    dear all, if i have 2 flip-flops , ff1 clock pin is connected to clk ff2 clock pin is connected to gated clock..... my doubt... if i found either hold r setup violation on this path with repsect to +ve edge.. then how i can fix the violation can any one guide me thanks in advance bhaskarg
  6. B

    to overcome hold vioation

    hi to all, am new to vlsi my doubt : example, if i have a slack -2.156 then adding buffer at that hold violating path is better or increasing the drive strength of that cell is better can any one guide me thanks in advance bhaskarg
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