Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
global net connections are used to define the pwr/gns nets to be connected to various pwr/gns pins of std cells/macros/IO Pads etc in your design.
Tie cell :
When any signal pins in your design has 1'b1(to be conncted to pwr net) and 1'b0 (to be connected to gnd) connections then, you need to...
As per my knowledge there is no cmd in Ecnounter corresponding for this.
The way, I have been doing it is by assigning higher net weight to all these nets.
Hi,
What u r observing is very common and obvious and known issue.
Wwireload models assign all the nets having same fanout as same delay which does not correlate with the real layout.
2 nets may have same numebr of fanout but those nets may have very diffrent netlength due to placement in...
apart from what jpvSoccer wrote..
congestion may be due to some high pin count cells, like you would observe congestion inside the GCELLs where AOI and other high pin count cells are placed.
Congestion may be in the small channels b/w the hard macros.
Congestion may be just below or worund...
wht i understand is that footprint means ... cells which have same intention or purpose..... like we say ... buffer footprint then that means all the cells which can be used as buffers..... when we say delay footprint then thats mean all the cells which can be used as inverters ....when we say...
Hi jpvSoccer,
I got this path closed after mapping and optimization.
But, What i want to know is that the timing summary which has been dumped by RC is dumped before it started actual mapping (as u can see the unmapped instance "dataram_rdata_lat_reg_03/d <<< unmapped_latch" in the report...
Wireload models are now old technique to estimate the net delay.
RC has come with better approach know as PLE (plysical layout estimation).
It give better correlation as per my experiments.
Hi Guys,
I had done just the elaboration in RC so, Now I assume my netlist to be in form of generic gates and in form of chipWare components. And, its NOT still mapped to technology library cell.
Now if I do report timing, then I get timing report like following and RC reported the slack also...
Hi Guys,
I am new to RC synthesis Tool.
While doing synth -to_map, RC dumps the global estimated target slack as :
========
Cost Group 'abc1' target slack: 59 ps
Target path end-point (Pin: top/abc/abc1/dataram_rdata_lat_reg_03/d)
Warning : Possible timing problems have been detected in...
Hi Guys,
Thanks for ur inputs.
In my flow, I have enabled the boundry optmization using "set_attr boundry_opto true" So, I beleive that optimiztion transforms/moves of Synthesis tool would nt be constrained by module's boundry - Is my undertanding correct ?
If Yes, then y do I need to do...
Hi Guys,
I am new to Synthesis and expert of backend flow.
I wanna know - hows does ungrouping helps in optimisation in RC Tool.
I have enables the boundry_opto for subDesigns.
But, still wanna know - the benfits of ungrouping in RC.
How to identify the candidates for ungrouping.
What all...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
