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Hi,
Macro cell -- This is a small level of layout design for Ex: LDO block, divider etc
Filler cell -- Cell used to filler the gap between the IO cells and to continue the power/gnd bus
ECO cell -- This cell has some extra devices which will be re used for improvements after the first cut tape...
Please find the answers in below
1.---> Change the metal tapping point to avoid EM in your case. Since tool is assuming that, the first contact will taking all current but that is not the case.
2. --> Antenna diode are required to discharge the charges accumulated on metals during the...
Hi,
Basics about VLSI or your academical VLSI or semiconductor books are fine.
Also read detail in resistance, capacitance and Inductance.
regards,
Basu
Hi,
You can use normal shielding and co-axial shielding depending upon the critical on those diff nets.
1. Normal shielding -- side by side
Metal2 is you conductor
Add M2 both side of the conductor with 1:2:1 spacing.
2. Co axial
Adding M3 on top sides with width to cover fully the...
Hi,
Please select the resistor depending upon
1. Resistance value
2. Noise immunity
3. isolation of nets
4. Voltage dividing
5. Current caring capability.
6. Thermal coefficient
Finlay, APPLICATION.
Please check with your requirement and select accordingly.
For ex:
15K --- Use POLY...
Hi,
First check with layout view is correct or not, then check the stream out.log file for the GDSII file generation without ERRORS and WARNINGS.
Then try with verification steps.
Basu
- - - Updated - - -
Hi,
Go to CIW window --> File --> Export-->Stream-->Fill the required options and...
Hi,
Please make sure that your library path is defined properly, cell name presence in that library and symbol views.
Browse all three things and Then you try with the adding instance.
Thanks,
Basu
Hi Nanda,
Diodes can be used for Antenna correction which are in reverse bias condition. So that, in normal mode wont affect the functionality.
1. PMOS gate
============
-->Add diode in Nwell, tie Nwell ( n terminal of diode) to VDD and gate node to signal (p terminal of diode). So now diode is...
Hi,
Metal are usually done by Copper and Silver Alloys.
VIA's are done by Tungeston materials to avoid ohmic contact issues.
Better understanding read any CMOS FABRICATION books.
Thanks and regards,
Basu
Hi,
Causes of EM violations are
1. In adequate metal widths use and skinny metal routing
2. Insufficient numbers of VIA's
3. Metal/VIA current carrying capability of used for power.signal routing like Thick and Thin metals in a tech.
4. Improper POWER BUS plan or POWER GRID plan
5. Not...
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