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Re: Metal slotting
it's needed for wide metal so that mechanical stress will be reduced. It will improve yield, but reduce your metal sheet resistance, hence increase voltage drop along the metal
Re: metal layers
if you use something like 11 layers of metal, usually the top level metal is aluminum not copper for reliability purpose in order to connect to solder bump(C4).
And if you design high performance dense chip, the capacitance between wires at same metal level is far larger than...
a common way to size transmission gate is to make both pmos and nmos the same size though this will make the rising edge delay and the falling edge delay different, but this is also true for dynamic logic and skewed cmos
It means your poly over diffusion can have ONLY one direction, and the preferred on is horizontal. This requirement is for printing exact narrow poly at 65nm node
stress effect due to bump: No clue... I don't think this can affect your transistor since bump is far away from your transistor. The stress may affect how you choose your top level interconnect and dielectric materials.
For deep submicron technology such as 65nm or 45nm, in general only one poly(active) direction is allowed. But for other not so deep submicron technology, it maybe OK for using 2 poly directions to those non-critical circuitry.
That may depends on what kind of circuitry you have. Usually you want to put circuitry sensitive to alpha particles far away from bumps, such as memory cells and flip-flop to reduce your soft-error rates.
Re: dummy metal filling
Due to CMP(chemical mechanical processing) on metal, with dummy metal you'll have
small variation(metal loss). This is very important especailly for deep submicron technology since your metal thickness is quite small.
The common practice for dummy metal is to connect it...
register file sram difference
In CPU related fields, register file is usually used for faster access to memory, multiport operation(such as read & write at the same time, or read out the memory content in multiple ports) which requires much smaller memory capacity(KB) and much larger memory...
cmos domino logic
For dynamic logic you also need to consider leakage, noise and clk skew related problems which become really hard problems in current deep submicron technology.
Circuits robustness is alway more important than speed, especially in technologies below 90nm.
Hi All,
I want to use Hspice to get Vth directly. I used .option list but not sure whether this is the right way to find out Vth for devices.
Any opinions?
Thanks.
Re: One question about clock
You should have extra clock skew for duty cycle variation. So for STA, you just need to add more clock skew if the time path includes both clk edges.
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